Abderazek Ben Abdallah The University of Aizu School of Computer Science and Engineering, 〒965-8580 Aizu-Wakamatsu, Japan コンピュータ理工学 公立大学法人会津大学 〒965-8580 福島県会津若松市一箕町鶴賀 Office: 202-A; Laboratory: 202-E-F Phone: 3224; E-mail: benab (at) u-aizu.ac.jp

Research Interests

• Power-efficient, Reliable Network-on-Chips (3D-TSV, Si-Photonics/SiPh, Hybrid)
  
• 3D-IC and Multi-die system architectures (Partitioning; SW mapping; Dynamic latency & performance analysis; Communication protocols; Power analysis)
• Neuromorphic Algorithms and Systems
• Computer architecture
• System-on-Chip (SoC) Architecture
• Distributed Energy and Micro-energy Harvesting
  

Publications

Journal papers

1. K. N. Dang, N. A. V. Doan, N. -D. Nguyen and A. B. Abdallah, "HeterGenMap: An Evolutionary Mapping Framework for Heterogeneous NoC-Based Neuromorphic Systems," in IEEE Access, vol. 11, pp. 144095-144112, 2023, doi: 10.1109/ACCESS.2023.3345168. keywords: {Neural networks;Neuromorphics;Genetic algorithms;Task analysis;Routing;Hardware;Synapses;Fault tolerance;Network-on-chip;Fault-tolerance;spiking neural network;neuromorphic system;network-on-chip;max flow;migration}, 

2. Y. Liang, Z. Wang and A. Ben Abdallah, "Robust Vehicle-to-Grid Energy Trading Method Based on Smart Forecast and Multi-Blockchain Network," in IEEE Access, vol. 12, pp. 8135-8153, 2024, doi: 10.1109/ACCESS.2024.3352631. keywords: {Vehicle-to-grid;Blockchains;Forecasting;Economics;Costs;Vehicle dynamics;Task analysis;Emissions trading;Energy management;Energy trading;vehicle-to-grid;energy forecast;multi-blockchain},

3. Z. Wang, M. Hisada and A. Ben Abdallah, "A Hybrid Clustered Approach for Enhanced Communication and Model Performance in Blockchain-Based Collaborative Learning," in IEEE Access, vol. 12, pp. 16975-16988, 2024, doi: 10.1109/ACCESS.2024.3359272. keywords: {Blockchains;Collaboration;Adaptation models;Federated learning;Voting;Solid modeling;Privacy;Edge computing;Homomorphic encryption;Blockchain-based;collaborative edge learning;privacy preservation;communication efficiency;robustness}

4. N. -D. Nguyen, A. B. Ahmed, A. Ben Abdallah and K. N. Dang, "Power-Aware Neuromorphic Architecture With Partial Voltage Scaling 3-D Stacking Synaptic Memory," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 31, no. 12, pp. 2016-2029, Dec. 2023, doi: 10.1109/TVLSI.2023.3318231. keywords: {Computer architecture;Stacking;Hardware;Memory management;Neuromorphics;Power demand;Threshold voltage;3-D-IC-based stacking memory;low-power;neuromorphic system;power-gating;spiking neural networks (SNNs);voltage scaling},

5. W. Y. Yerima, K. N. Dang and A. B. Abdallah, "R-MaS3N: Robust Mapping of Spiking Neural Networks to 3D-NoC-Based Neuromorphic Systems for Enhanced Reliability," in IEEE Access, vol. 11, pp. 94664-94678, 2023, doi: 10.1109/ACCESS.2023.3311031. keywords: {Neurons;Hardware;Neuromorphics;Fault tolerant systems;Circuit faults;Reliability;Three-dimensional displays;Clustering methods;Reliable neuromorphic;mapping;neural reuse;3D-NoC;clustering},

6. N. -D. Nguyen, X. -T. Tran, A. B. Abdallah and K. N. Dang, "An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture," in IEEE Access, vol. 11, pp. 82377-82389, 2023, doi: 10.1109/ACCESS.2023.3301560. keywords: {Hardware;Computer architecture;Neurons;Biological neural networks;Three-dimensional displays;Power demand;Neuromorphic engineering;Spiking neural network;3D IC-based stacking memory;digital neuromorphic},

7. W. Y. Yerima, O. M. Ikechukwu, K. N. Dang and A. Ben Abdallah, "Fault-Tolerant Spiking Neural Network Mapping Algorithm and Architecture to 3D-NoC-Based Neuromorphic Systems," in IEEE Access, vol. 11, pp. 52429-52443, 2023, doi: 10.1109/ACCESS.2023.3278802. keywords: {Neurons;Hardware;Circuit faults;Neuromorphics;Fault tolerant systems;Synapses;Biological neural networks;Neuromorphic;fault-tolerant;neuron mapping;selection and ranking;3D-NoC},

8. Y. Liang, Z. Wang and A. B. Abdallah, "V2GNet: Robust Blockchain-Based Energy Trading Method and Implementation in Vehicle-to-Grid Network," in IEEE Access, vol. 10, pp. 131442-131455, 2022, doi: 10.1109/ACCESS.2022.3229432. keywords: {Blockchains;Vehicle-to-grid;Security;Peer-to-peer computing;Microgrids;Games;Time factors;Electric vehicles;Energy management;Energy trading;electric vehicles;robustness;vehicle-to-grid},

9. Wang, Jiangkun, Ogbodo Mark Ikechukwu, Khanh N. Dang, and Abderazek Ben Abdallah, "Spike-Event X-ray Image Classification for 3D-NoC-Based Neuromorphic Pneumonia Detection" Electronics 11, no. 24: 4157. https://doi.org/10.3390/electronics11244157. Keywords: spiking neural network; neuromorphic; reconfigurable; fault-tolerant; pneumonia; edge

10. Z. Wang and A. Ben Abdallah, "A Robust Multi-Stage Power Consumption Prediction Method in a Semi-Decentralized Network of Electric Vehicles," in IEEE Access, vol. 10, pp. 37082-37096, 2022, doi: 10.1109/ACCESS.2022.3163455. keywords: {Blockchains;Collaborative work;Power demand;Electric vehicles;Computational modeling;Vehicle-to-grid;Renewable energy sources;AI-enabled;blockchain-based;robust;power-management;EVs;smart grid},

11. K. N. Dang, N. A. V. Doan and A. Ben Abdallah, "MigSpike: A Migration Based Algorithms and Architecture for Scalable Robust Neuromorphic Systems," in IEEE Transactions on Emerging Topics in Computing, vol. 10, no. 2, pp. 602-617, 1 April-June 2022, doi: 10.1109/TETC.2021.3136028. keywords: {Neurons;Costs;Neuromorphics;Complexity theory;Hardware;Genetic algorithms;Error analysis;Fault-tolerance;spiking neural network;neuromorphic system;network-on-chip;max flow;migration},

12. Abderazek Ben Abdallah, Khanh N. Dang, “Toward Robust Cognitive 3D Brain-inspired Cross-paradigm System,'' Frontier in Neuroscience 15:690208, doi: 10.3389/fnins.2021.690208

13. K. N. Dang, A. B. Ahmed, A. B. Abdallah and X. -T. Tran, "HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 4, pp. 799-812, April 2022, doi: 10.1109/TCAD.2021.3069370. keywords: {Through-silicon vias;Reliability;Circuit faults;Redundancy;Integrated circuit reliability;Fault tolerant systems;Cooling;3D-Network on Chips (3D-NoCs);architecture and design;fault-tolerance;maximum flow minimal cut;reliability;through silicon vias (TSVs)},

14. O. M. Ikechukwu, K. N. Dang and A. B. Abdallah, "On the Design of a Fault-Tolerant Scalable Three Dimensional NoC-Based Digital Neuromorphic System With On-Chip Learning," in IEEE Access, vol. 9, pp. 64331-64345, 2021, doi: 10.1109/ACCESS.2021.3071089. keywords: {Neuromorphics;Neurons;Three-dimensional displays;Synapses;Computer architecture;Two dimensional displays;Fault tolerant systems;Digital neuromorphic;spiking neural network;fault-tolerant;3D-NoC;architecture},

15. K. N. Dang, A. B. Ahmed, A. B. Abdallah and X. -T. Tran, "TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 672-685, March 2020, doi: 10.1109/TVLSI.2019.2948878. keywords: {Through-silicon vias;Built-in self-test;Time factors;Task analysis;Fault tolerance;Fault tolerant systems;Error correction code (ECC);fault localization;fault tolerance;through-silicon via (TSV);product code},

16. Z. Wang, M. Ogbodo, H. Huang, C. Qiu, M. Hisada and A. B. Abdallah, "AEBIS: AI-Enabled Blockchain-Based Electric Vehicle Integration System for Power Management in Smart Grid Platform," in IEEE Access, vol. 8, pp. 226409-226421, 2020, doi: 10.1109/ACCESS.2020.3044612. keywords: {Artificial intelligence;Security;Vehicle-to-grid;Power generation;Blockchain;Training;Power system management;AI-enabled;blockchain-based;EVs;power-management;AI-chip;virtual power plant},

17. K. N. Dang, A. B. Ahmed, A. B. Abdallah and X. -T. Tran, "A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems," in IEEE Access, vol. 8, pp. 166642-166657, 2020, doi: 10.1109/ACCESS.2020.3022904. keywords: {Through-silicon vias;Redundancy;Circuit faults;Testing;Fault tolerant systems;Fault-tolerance;fault detection;parity check;through silicon via;real-time;thermal aware},

18. K. N. Dang, A. B. Ahmed, Y. Okuyama and A. B. Abdallah, "Scalable Design Methodology and Online Algorithm for TSV-Cluster Defects Recovery in Highly Reliable 3D-NoC Systems," in IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 3, pp. 577-590, 1 July-Sept. 2020, doi: 10.1109/TETC.2017.2762407. keywords: {Through-silicon vias;Redundancy;Fault tolerant systems;Integrated circuit reliability;Routing;3D-NoCs;fault-tolerance;reliability;architecture and design;TSV-cluster defects},

19. K. N. Dang, M. C. Meyer, A. B. Ahmed, A. B. Abdallah and X. -T. Tran, "A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip," in IEEE Access, vol. 8, pp. 59571-59589, 2020, doi: 10.1109/ACCESS.2020.2982836. keywords: {Through-silicon vias;Testing;Circuit faults;Encoding;Wires;Fault tolerance;3D-ICs;fault-tolerance;error correction code;through-silicon-via;product code;parity check;networks-on-chip;fault-detection},

20. The H. Vu,Yuichi Okuyama, Abderazek Ben Abdallah, “Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithms and Architecture for 3D-NoC of Spiking Neurons,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Special Issue on Hardware and Algorithms for Learning On-a-chip for Energy-Constrained On-Chip Machine Learning, Vol. 15, No. 4, Article 34, October 2019. doi: 10.1145/3340963

21. T. H. Vu, O. M. Ikechukwu and A. Ben Abdallah, "Fault-Tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems," in IEEE Access, vol. 7, pp. 90436-90452, 2019, doi: 10.1109/ACCESS.2019.2925085. keywords: {Neurons;Routing;Fault tolerance;Fault tolerant systems;Computer architecture;Hardware;Biological neural networks;Spiking neural networks;performance assessment;fault-tolerant;k-means based multicast routing;scalable architecture},

22. The H. Vu, Yuichi Okuyama, Abderazek Ben Abdallah, ‘’Analytical performance assessment and high‑throughput low‑latency spike routing algorithm for spiking neural network systems,’’ Journal of Supercomputing 75, pp. 5367–5397 (2019). https://doi.org/10.1007/s11227-019-02792-y Keywords: {Analytical assessment;3DNoC-SNN; Low-latency multicast algorithm; Spiking neural network}

23. Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”SAFT-PHENIC: a thermal-aware microring fault-resilient photonic NoC,” The Journal of Supercomputing, Volume 74, Issue 9, pp 4672–4695, 2018. DOI: 10.1007/s11227-018-2463-x Keywords: {Fault tolerant; Optical router; NoCs ; High performance ; Many-coresystems ; Microring ; Thermal variation}

24. Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue: 11, pp. 3099 – 3112, vol. 2017.  DOI: 10.1109/TVLSI.2017.2736004. keywords: {Analytical models;Fault tolerance;Fault tolerant systems;Routing;Reliability engineering;Very large scale integration;Analytical model;architecture and design;fault tolerance;reliability analysis},

25. A. B. Ahmed, T. Yoshinaga and A. Ben Abdallah, "Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism," in IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 2, pp. 533-544, 1 April-June 2020, doi: 10.1109/TETC.2017.2737016. keywords: {Photonics;Computer architecture;Routing;Optical switches;Bandwidth;Optical waveguides;Analytical models;Many-cores;scalability;photonic;Network-on-Chip;wavelength-shifting;routing},

26. Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Low-overhead Soft-Hard Fault Tolerant Architecture, Design and Management Scheme for Reliable High-performance Many-core 3D-NoC Systems,” Journal of Supercomputing (2017) 73:2705–2729. Keywords: {3D NoCs;Fault-tolerance; Soft–hard faults; Reliability; Architecture · Design}

27. Achraf Ben Ahmed, A. Ben Abdallah, ''Architecture and Design of Real-Time Systems for Elderly Health Monitoring,'' Journal of Embedded Systems, 2017, Vol.9, No.5, pp.484 – 494,  DOI: 10.1504/IJES.2017.10007717. Keywords {Hybrid silicon-photonic NoC · Energy-efficient · Non-blocking photonic switch · Contention-aware · Path configuration}

28. Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems,” The Journal of Supercomputing, Volume 73, Issue 4, pp 1567–1599 , April 2017. doi: 10.1007/s11227-016-1846-0. Keywords{Fault tolerant · Optical router · NoCs · High performance ·Many-core systems · Microring}

29. Achraf Ben Ahmed, Abderazek Ben Abdallah,''An Energy-Efficient High-Throughput Mesh-Based Photonic On-Chip Interconnect for Many-Core Systems,'' Photonics 2016, 3(2), 15; https://doi.org/10.3390/photonics3020015. Keywords{ energy efficient; contention aware; photonic NoC; non-blocking photonic switch; path-configuration; many-core SoCs; high-performance}

30. Akram Ben Ahmed, Abderazek Ben Abdallah, ”Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC Systems”, Journal of Parallel and Distributed Computing, Volumes 93–94, July 2016, Pages 30-43, ISSN 0743-7315, doi:10.1016/j.jpdc.2016.03.014. Keywords {3D NoC ; Fault-tolerance ; Robustness ; Architecture ; Dynamic reconfiguration ;Deadlock-free}

31. Achraf Ben Ahmed, Abderazek Ben Abdallah, “Hybrid Silicon-Photonic Network-on-Chip for Future Generations of High-performance Many-core Systems,” The Journal of Supercomputing, Dec. 2015, Vol. 71, Issue 12, pp 4446-4475. DOI: 10.1007/s11227-015-1539-0. Keywords {Hybrid silicon-photonic NoC · Energy-efficient · Non-blocking photonic switch · Contention-aware · Path configuration}

32. Akram Ben Ahmed, A. Ben Abdallah,”Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures,” Journal of Parallel and Distributed Computing, 74/4 (2014), pp. 2229-2240. Keywords {3D-NoC; Architecture; Parallel; Adaptive; Look-ahead routing; Deadlock-free}

33. Akram Ben Ahmed, A. Ben Abdallah, ”Architecture and Design of High-throughput, Low-latency and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip,” The Journal  of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532. Keywords{3D-NoC ;
    Architecture;
    Fault-tolerance;
    Look-ahead Routing}

34. Abderazek Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, “Natural Instruction Level Parallelism-aware Compiler for High-Performance QueueCore Processor Architecture,” The Journal of Supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.

35. Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Compiling for Reduced Bit-Width Queue Processors,” Journal of Signal Processing Systems, Volume 59, Number 1, 45-55, 2010.

36. Arquimedes Canedo, Abderazek Ben Abdallah,  Masahiro Sowa, “Efficient Compilation for Queue Size-Constrained Queue Processors”, Journal of Parallel Computing, Vol.35, pp. 213-225, 2009. Key words{Queue Register File, Queue Processor, Constrained, Optimization,Compiler}

37. Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Design and Implementation of a Queue Compiler”, Journal of Microprocessors and Microsystems, Vol. 33, Issue 2, pp. pp. 29-138, 2009.

38. Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Compiler Support for Code Size Reduction using a Queue-based Processor”, Transactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009. Keywords {Code Generation, Code Size Reduction, Reduced bit-width Instruction Set, Queue Computation Model}

39. Abderazek Ben Abdallah, A. Canedo, T. Yoshinaga, M. Sowa, “The QC-2 Parallel Queue Processor Architecture,” Jnl. of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008. Keywords{Queue computing; Queue processor; Parallel; Design; Circular queue-register}

40. Md. Musfiquzzaman Akanda, Abderazek Ben Abdallah, and Masahiro Sowa, “Dual-Execution Mode Processor Architecture,” The Journal of Supercomputing, Vol. 44, No. 2, pp. 103-125, 2008. Keywords{Dual-execution · Queue computation · Dynamic switching · Embedded core · Hardware usability · Parallel}

41. A. Acanda, Ben Abdallah, and M. Sowa, “A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model,”  Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007. Keywords{Code Generation; Algorithms; Queue Computation; Level DAG}

42. A. Ben Abdallah, and M. Sowa, “Advanced Power Management Techniques for Mobile Communication Systems,” Journal of Computer Research, Vol. 14, No.2, pp. 109-128, 2007. Key Words{mobile computing, power optimizations techniques, energy, managements.}

43. Md. Musfiquzzaman Akanda, A. Ben Abdallah, and M. Sowa, “Dual-Execution Mode Processor Architecture For Embedded Applications,” Journal of Mobile Multimedia, Vol. 3, No.4, Dec. 2007, pp. 347-370. Keywords{Dual-Execution Mode; Queue Computation; Dynamic Switching Mechanism;Embedded Core.}

44. A. Ben Abdallah, T. Yoshinaga, M. Sowa, “High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core,” The Journal of Supercomputing, Vol. 38, Number 1, pp. 3-15, 2006. Keywords{QueueCore, Queue computing, design, modular design, simple}

45. Abderazek Ben Abdallah, Sotaro Kawata, Masahiro Sowa, “Design and Architecture for an Embedded 32-bit Queue Core,” Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006. Keywords{QueueCore, Queue computing, design, modular design, simple}

46. Viet, T. Yoshinaga, A. Ben Abdallah, and Masahiro Sowa, “Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters,” IPSJ Transactions on Advanced Computing Systems, Vol.46, pp.25-37, Jan. 2005. Keywords {Hybrid MPI-OpenMP; SMP; Clusters; Architecture}

47. M. Sowa, A. Ben Abdallah, and T. Yoshinaga, “Parallel Processor Architecture Based on Produced Order Computation Model,” The Journal of Supercomputing, Vol. 32, No. 3, pp. 217-229, June 2005. Keywords{produced order, queue processor, high performance, circular queue-registers, design}

48. Abderazek Ben Abdallah, Mudar Sarem, Masahiro. Sowa, “Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors,” IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000. keywords: {precise interrupt, write-once, paral lel, register re-naming, out-of-order}

Conference Papers

1. Jiangkun Wang, Khanh N. Dang and Abderazek Ben Abdallah, “Scaling Deep-Learning Pneumonia Detection Inference on a Reconfigurable Self-Contained Hardware Platform”, 2023 IEEE 6th International Conference on Electronics Technology (ICET), May 12-15, 2023. Best Student Paper Award.

2. Mohamed Maatar, Khanh N. Dang and Abderazek Ben Abdallah, “Thermal-Aware Task-Mapping Algorithm and Architecture for 3D-NoC-Based Event-Driven Neuromorphic System”, 2023 IEEE 6th International Conference on Electronics Technology (ICET), May 12-15, 2023.

3. Cheng Hong, Sinchhean Phea, Khanh N. Dang, Abderazek Ben Abdallah, ''The AIzuHand Neuromorphic Prosthetic Hand,'' ETLTC2023, January 24-27, 2023

4. Yamato Saikawa, Khanh N. Dang, Abderazek Ben Abdallah, ''Multimodal sEMG and Speech-Based Design and Evaluation of a Low-Cost'', ETLTC2023, January 24-27, 2023

5. Yu Yajima, Zhishang Wang, Abderazek Ben Abdallah, ''Robust Collaborative Learning Against Poisoning Attacks in Electric Vehicles Network,'' ETLTC2023, January 24-27, 2023

6. Mark Ogbodo, Abderazek Ben Abdallah, ''Study of a Multi-modal Neurorobotic Prosthetic Arm Control System based on Recurrent Spiking Neural Network,'' ETLTC2022, January 25-28, 2022

7. Yamato Saikawa, Abderazek Ben Abdallah, ''Study of Deep Learning-based Hand Gesture Recognition Toward the Design of a Low-cost Prosthetic Hand'',  ETLTC2022, January 25-28, 2022

8. Masaki Watanabe, Abderazek Ben Abdallah, ''A Low-cost Raspberry Pi-based Control System for Upper Limb Prosthesis,''  ETLTC2022, January 25-28, 2022

9. Sinchhean Phea, Abderazek Ben Abdallah, ''An Affordable 3D-printed Open-Loop Prosthetic Hand Prototype with Neural Network Learning EMG-Based Manipulation for Amputees,''  ETLTC2022,  January 25-28, 2022

10. Yuuki Okada, Jiangkun Wang, Tomohide Fukuchi and Abderazek Ben Abdallah, ''Parallelization and Hardware Mapping of Deep Neural Network on Re-configurable Platform for AI-Enabled Biomedical System,'' ETLTC2022, January 25-28, 2022

11. Ogbodo Mark Ikechukwu, Khanh N. Dang and Abderazek Ben. Abdallah, “Energy-efficient Spike-based Scalable Architecture for Next-generation Cognitive AI Computing Systems,” Springer Lecture  Note in Computer Science (LNCS), International Symposium on Ubiquitous Networking 2021 (UNET21), May 19 – May 22, 2021, Marakesh, Morocco (Best Student Paper Award)

12. Naoto Ageishi, Fukuchi Tomohide, Abderazek Ben Abdallah, ''Real-time Hand-Gesture Recognition based on Deep Neural Network,'' 3rd  ETLTC2021 -ACM Chapter Int. Conference  on Information and Comm. Technology, January 27-30, 2021, Aizu-Wakamatsu, Japan, SHS Web of Conferences 102, 04009 (2021),  10.1051/shsconf/202110204009

13. Miyuka Nakamura, Jiangkun Wang, Sinchhean Phea, Abderazek Ben Abdallah, ''Comprehensive Study of Coronavirus Disease 2019 (COVID-19) Classification based on Deep Convolution Neural Networks,'' 3rd  ETLTC2021-ACM Chapter Int. Conference  on Information and Comm. Technology, January 27-30, 2021, Aizu-Wakamatsu, Japan, SHS Web of Conferences 102, 04007 (2021), DOI:10.1051/shsconf/202110204007

14. Okada Yuuki, Jiangkun Wang, Ogbodo Mark Ikechukwu, Abderazek Ben Abdallah, ''Hardware Acceleration of Convolution Neural Network for AI-Enabled Realtime Biomedical System,'' 3rd  ETLTC2021-ACM Chapter Int. Conference  on Information and Comm. Technology,   January 27-30, 2021, Aizu-Wakamatsu, Japan, SHS Web Conf., 102 (2021) 04019, DOI:10.1051/shsconf/202110204019

15. Sinchhean Phea, Zhishang Wang, Jiangkun Wang, Abderazek Ben Abdallah, ''Optimization and Implementation of a Collaborative Learning Algorithm for an AI-Enabled Real-time Biomedical System,'' 3rd  ETLTC2021-ACM Chapter Int. Conference  on Information and Comm. Technology, January 27-30, 2021, Aizu-Wakamatsu, Japan, SHS Web Conf., 102 (2021) 04017, DOI: 10.1051/shsconf/202110204017  (Best Paper Award)

16. H. Huang, M. Ogbodo, Z. Wang, C. Qiu, M. Hisada and A. Ben-Abdallah, "Smart Energy Management System based on Reconfigurable AI Chip and Electrical Vehicles," 2021 IEEE International Conference on Big Data and Smart Computing (BigComp), Jeju Island, Korea (South), 2021, pp. 233-238, doi: 10.1109/BigComp51126.2021.00051.

17. Khanh N. Dang, Akram Ben Ahmed, Fakhrul Zaman Rokhani, Abderazek Ben Abdallah, and Xuan-Tu Tran, ‘‘A thermal distribution, lifetime reliability prediction and spare TSV insertion platform for stacking 3D NoCs’’, 2020 International Conference On Advanced Technologies For Communications (ATC), Nov. 8-10, 2020, Nha Trang, Vietnam

18. Tomohide Fukuchi, Ogbodo Mark Ikechukwu,  Abderazek Ben Abdallah. ''Design and Optimization of a Deep Neural Network Architecture for Traffic Light Detection,'' ACM Chapter International Conference on Educational Technology, Language and Technical Communication (ETLTC), January 27-31, 2020, Aizuwakamatsu, Japan.

19. Ogbodo Mark Ikechukwu, Khanh N. Dang, Tomohide Fukuchi, Abderazek Ben Abdallah, “Architecture and Design of a Spiking Neuron Processor Core Towards the Design of a Large-scale Event-Driven 3D-NoC-based Neuromorphic Processor”, ACM Chapter International Conference on Educational Technology, Language and Technical Communication (ETLTC), January 27-31, 2020, Aizuwakamatsu, Japan.

20. Mark Ogbodo, The Vu, Khanh N. Dang and Abderazek Abdallah, “Light-weight Spiking Neuron Processing Core for Large-scale 3D-NoC based Spiking Neural Network Processing Systems”, The 7th IEEE International Conference on Big Data and Smart Computing, Feb 19, 2020 - Feb 22, 2020,  Pusan, South Korea

21. Khanh N. Dang and Abderazek Ben Abdallah “An Efficient Software-Hardware Design Framework for Spiking Neural Network Systems”, 2019 IEEE International Conference on Internet of Things, Embedded Systems and Communications (IINTEC 2019), Tunis, Tunisia, 2019, pp. 155-162. DOI: 10.1109/IINTEC48298.2019.9112123

22. Khanh N. Dang, Michael Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, and Xuan-Tu Tran, “2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults”, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2019), Nov. 11-14, 2019.

23. Khanh N. Dang, Akram Ben Ahmed, Ben Abdallah Abderazek and Xuan-Tu Tran, “TSV-IaS: Analytic analysis and low-cost non-preemptive on-line detection and correction method for TSV defects'', IEEE Symposium on VLSI (ISVLSI) 2019, pp. 301-306, Jul. 15-17, 2019 . DOI: 10.1109/ISVLSI.2019.00096

24. The H. Vu, Abderazek Ben Abdallah, ''A Low-latency K-means based Multicast Routing Algorithm and Architecture for Three Dimensional Spiking Neuromorphic Chips'', IEEE International Conference on Big Data and Smart Computing (BigComp 2019), Kyoto, Japan, Feb 28 - Mar 2, 2019  [Best Paper Award]

25. The H. Vu, Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro-inspired Architecture in Hardware”, IEEE International Conference on Big Data and Smart Computing  (BigComp 2018), Shanghai, China, January 15-18, 2018.

26. Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D NoC System”, 25th IEEE Asian Test Symposium (ATS’16), November 21-24, 2016

27. Khanh N. Dang, Yuichi Okuyama, Abderazek Ben Abdallah, ”Soft-Error Resilient Network-on-Chip for Safety-Critical Applications”, 2016 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), June 27 – 29, 2016  

28. Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, “A Soft-Error Resilient 3D Network-on-Chip Router for Highly-reliable Multi-core Systems”, IEEE 7th International Conference on Awareness Science and Technology (iCAST 2015), Sep. 22-24, 2015.

29. Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Hybrid Photonic NoC based on Non-blocking Photonic Switch and Light-weight Electronic Router”, Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015.

30. Michael Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Optical Router for Reliable Network-on-Chip Systems”, Proc. of 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs (MCSoC-15), Sept. 2015.

31. Michael Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Fault-tolerant Photonic Network-on-Chip,” Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015.

32. Achraf Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah,”Non-blocking Electro-optic Network-on-Chip Router for High-throughput and Low-power Many-core Systems”,  Proc. of the World Congress on Information Technology and Computer Applications 2015, June 11-13, 2015

33. Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah,”Efficient Router Architecture, Design and Performance Exploration for Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC)”, Proc. Of the International Conference on Information Science and Control Engineering, 04/2015.

34. Achraf  Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, ”Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems”, IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Manycore SoCs (MCSoC-14), pp. 197-2014, Sept. 2014.

35. Achraf Ben Ahmed, A. Ben Abdallah, ”PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-throughput Many-core Systems-on-Chip”, IEEE Proceedings of the 14th International Conference on Sciences and Techniques of Automatic control and computer engineering, 2013

36. Akram Ben Ahmed, A. Ben Abdallah, ”Fault-tolerant Routing Algorithm with Deadlock Recovery Support for 3D-NoC Architectures”, IEEE Proceedings of the 7th International Symposium on Embedded Multicore SoCs, Sept. 2013

37. Achraf Ben Ahmed, A. Ben Abdallah, ”Hardware/Software Prototyping of Dependable Real-Time System for Elderly Health Monitoring”, IEEE Proc. of the World Congress on Computer and IT, ICMAES, June 2013.

38. Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ”Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era”, Proc. IEEE 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013′), July 2013.

39. Akram Ben Ahmed, A. Ben Abdallah, ”Low-overhead Routing Algorithm for 3D Network-on-Chip”, IEEE Proc. of The Third International Conference on Networking and Computing (ICNC’12), pp. 23-32, 2012.

40. Akram Ben Ahmed, A. Ben Abdallah, ”LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture”, IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012.

41. Achraf Ben Ahmed, Yumiko Kimezawa, A. Ben Abdallah, ”Towards Smart Health Monitoring System for Elderly People”, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 248-253, 2012.

42. Akram Ben Ahmed, A. Ben Abdallah, ”ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications”, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012.

43. A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, ”Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoCs”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010. [Best Paper Award]

44. K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ”Advanced Design Issues for OASIS Network-on-Chip Architecture”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.

45. M. Masuda, A. Ben Abdallah, A. Canedo, ”Software and Hardware Design Issues for Low-Complexity High-Performance Processor Architecture”, IEEE ICPPW’09 Proc. of the 2009 International Conference on Parallel Processing Workshops, pp. 558-565, 2009.

46. Y. Haga, A. Ben Abdallah, and K. Kuroda, ”Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing”, The 19th Intelligent System Symposium (FAN 2009), pp.298-303, Sep. 2009.

47. S. Miura, A. Ben Abdallah, and K. Kuroda, ”PNoC – Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration”, The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep. 2009.

48. K. Mori, A. Ben Abdallah, and K. Kuroda, ”Design and Evaluation of a Complexity-Effective Network-on-Chip Architecture on FPGA”, The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009.

49. M. Masuda, A. Canedo, A. Ben Abdallah, ”Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture”, The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009. (Best Presentation Award).

50. T. Maekawa, A. Ben Abdallah, and K. Kuroda, ”Single Instruction Dual-Execution Model Processor Architecture”, Proc. IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008), pp.30-36, Dec. 2008.

51. H. Hoshino, A. Ben Abdallah, and K. Kuroda, ”Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model”, IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.

52. A. Canedo, A. Ben Abdallah, and M. Sowa, ”Quantitative Evaluation of Common Sub-expression Elimination on Queue Machines”, Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.

53. Arquimedes Canedo, Ben Abdallah Abderazek, Masahiro Sowa, ''New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP,'' 8th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), Adelaide, Australia, Dec. 3-6, 2007 (Best Paper Award)

54. A. Ben Abdallah, T Yoshinaga, and M. Sowa, ”Mathematical Model for Multiobjective Synthesis of NoC Architectures”, IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 2007.

55. A. Canedo, A. Ben Abdallah, and M. Sowa, ”Queue Register File Optimization Algorithm for QueueCore Processor”, Proc. IEEE 19th International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.

56. A. Canedo, A. Ben Abdallah, and M. Sowa, ”An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model”, Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007

57. A. Canedo, A. Ben Abdallah, and M. Sowa, ”Compiler Framework for an Embedded 32-bit Queue Processor”, Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.

58. A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Scalable Core-Based Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC (MCSoC)”, Proc. IEEE 35th International Conference on Parallel Processing Workshops, Aug. 14-18th, pp. 345-352, 2006.

59. A. Ben Abdallah, Masahiro Sowa, ”Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization”, Proc. of the Joint Symposium on Science, Society and Technology (JASSST2006), pp. 1-7, Dec. 4-9th, 2006.

60. A. Ben Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core”, Proc. of International Conference on Embedded and Ubiquitous Computing(EUC2005), LNCS Vol.3824, pp. 340-349, 2005.

61. M. Akanda, A. Ben Abdallah, S. Kawata, and M. Sowa, ”An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture”, Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 77-86, Dec. 2005.

62. A. Markovskij, A. Ben Abdallah, S. Kawata, and M. Sowa, ”Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation”, Proc. of the 38th International Symposium on Microarchitecture (MICRO-38), Nov. 2005.

63. Ta Quo Viet, T. Yoshinaga, and A Ben Abdallah, ”Performance Enhancement for Matrix Multiplication on an SMP PC Cluster”, Summer United Workshops on Parallel, Distributed and Cooperative Processing, August 2005.

64. A. Ben Abdallah, Markov Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme”, Proc. IEEE of the 7th High-Performance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.

65. Shigeta, L.-Q. Wang, N. Yagishita, A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”QJava: Integrate Queue Computational Model into Java”, Proc. of the Joint Japan-Tunisia Workshop on Computer Systems and Information Technology (JT-CSIT’04), July 2004.

66. A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, ”Design of Producer-Order Parallel Queue Processor Architecture”, Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.

67. M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”High-performance Hybrid Processor Architecture with Efficient Hardware Usability”, Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.

68. H. Sasaki, Y. Okumura, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Theoretical Evaluation of Simultaneous Multi-threading Parallel Queue Processor Architecture”, Proc. International Conference on Circuits/Systems, Computers and Communications, July 2004.

69. A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”On the Design of a Register Queue-Based Processor Architecture (FaRM-rq)”, Proc. of the International Symposium of Parallel and Distributed Processing and Applications (ISPA 2003), pp.248-262, July 2003.

70. L. Q. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java Bytecode”, Proc. of International Technical Conference in Circuits/Systems, Computers and Communications (ITC-CSCC2003), pp. 900-903, July 2003.

71. Tao. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPP”, SACSIS03, pp.299-306, 2003.

72. T. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPs”, Proc. of Symposium on Advanced Computing Systems and Infrastructures, pp.299-306, 2003.

73. A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Complexity Analysis of a Functional Assignment Register Microprocessor”, Proc. of the Int. Workshop on Modern Science and Technology (IWMST02), pp.116-123, Sep. 2002.

74. Kiriuka Nikolova, A. Ben Abdallah, and M. Sowa, ”Dynamical Critical Path Parallelism-Independent Scheduling Algorithm for Distributed Computing Systems”, Proc. of the International Technical Conference on Circuits and Systems, Computers and Communications, pp. 929-934, July 2001.

75. A. Ben Abdallah, and M. Sowa, ”DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor”, Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT’99), pp.131-136, October 1999.

76. A. Ben Abdallah, M. Sarem, and M. Sowa, ”A Survey on the advances of Disc I/O performance metrics”, Proc. of International Conference on Robotics, Vision and Parallel Processing, pp. 522-527, July 1999.

77. L. L. Shan, L. Liu, and A. Ben Abdallah, ”The Master-Slave Two Level Distributed Microcomputer Measuring and Monitoring System”, ISMTIT, Japan, pp. 161-164, 1996

Domestic Conference Papers

1.  Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Animal Recognition and Identification with Deep Convolutional Neural Networks for Farm Monitoring”, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018 

2. Yuji Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”SRAM Based Neural Network System for Traffic-Light Recognition in Autonomous Vehicles”, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018

3. Kanta Suzuki, Yuichi Okuyama, Abderazek Ben Abdallah, ”Hardware Design of a Leaky Integrate and Fire Neuron Core Towards the Design of a Low-power Neuro-inspired Spike-based Multicore SoC”, Information Processing Society  Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018

4. A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing”, Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.

5. A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, ”PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL”, Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.

6. T. Viet, T. Toshinga, A. Ben Abdallah, and M. Sowa, ”Optimization for Hybrid MPI-OpenMP Programs on a Cluster of SMPs”, SACSIS 2004.

7. A. Musfiquzzaman, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Computation Mechanism For Parallel Execution in Parallel Queue Processor”, Proc. of Information Processing Society of Japan, Vol. 60, pp. 3F-4, 2004.

8. A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)”, Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.

9. L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Fast, Effective Instruction Generation Algorithm For Queue-Java Compiler (QJAVAC)”, Proc. of Information Processing Society of Japan, Vol.2003, No.40, pp.55-60, 2003.

10. L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”An Ambiguous Context-Free Grammar for Deterministic Parsing In Queue-Java Compiler”, Proc. of Information Processing Society of Japan, Vol.2003, No.62, pp.7-12, 2003.

11. L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java”, Proc. of IIEICE Technical Conference, 2003.

12. A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, ”FARM QUEUE MODE: On a Practical Queue Execution Model (QEM)”, TIWSS’01, October 2001. 

13. A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARM-Queue Execution Model: Towards an Alternative Computing Paradigm”, Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000. 

14. A. Ben Abdallah, M. Sarem., and M. Sowa, ”Acyclic DFG on a Queue Machine”, Proc. of JSPP, Tokyo, pp.119-120, 2000.

15. A. Ben Abdallah, and M. Sarem, ”Instruction Scheduling System for Superscalar Processor”, JSPP, Tokyo, pp.161, Apr. 2000.

Invited Talks, Courses, Seminars

1. Invited talk, ''AI-powered, Fault-tolerant, and Low-power Systems for Healthcare Applications'', 2nd Symposium on the Use of AI in Healthcare Handling of Personal Information and Privacy, March 14-16, 2023
   

2. Invited talk,''Brain-inspired Systems for AI in the Edge'', kick-off ceremony of a collaboration project between JICA (Japan International Cooperation Agency), UoA-ISTIC, University of Carthage, Tunis, January 23, 2023

3. Special Talk, Introduction of University of Aizu Energy-Related Research [会津大学エネルギー関係研究紹介], 京都工芸繊維大学様との意見交換会, October 27, 2022
   

4. Invited Speaker, ''Neuromorphic Computing: Beyond-CMOS Approach to Future Computing'', 20th international conference on Sciences and Techniques of Automatic control and computer engineering (STA'2020), December 20-22, 2020, Monastir, Tunisia (Online talk due to COVID-19)

5. Invited talk, ''Energy Management System based on High-speed, Low-power AI-Chip, and Electrical Vehicles (EVs)'', Third Symposium on AI Center will be held on Saturday, Universoty of Aizu, Aizu-Wakamatsu, November 23, 2019.

6. Keynote Speaker , ''The Future of Machine Learning: Neuromorphic Chips,'' ACM 5th International Conference of Computing for Engineering and Sciences, Hammamet, 20-22 July 2019

7. Invited Speaker, ''Neuromorphic Computing Chips for AI at the Edge'', Machine Learning and Data Analytics Symposium (MLDAS 2019), March 1-2, Doha, 2019

8. Keynote Speaker, ''Artificial Intelligence Chips for Intelligent Systems'', 2019 International Conference on Intelligent Autonomous Systems (ICoIAS’2019), Singapore, 2019

9. Invited Talk, ''Artificial Intelligence Chips: From Data Centers to Edge and IoT Computing'', 2nd Symposium on AI Center, The University of Aizu, December 8, 2018. 

10. Keynote Speech, ''Neuro-inspired Computing Systems & Applications'', 2018 International Conference on Intelligent Autonomous Systems (ICoIAS’2018), Singapore, March 1-3, 2018

11. Invited Talk, ''Developing a Mindset for Innovation & Entrepreneurship'', 1st ACM Chapter Networking Seminar on Globalization & Innovative Thinking, 2017/11/26, University of Aizu

12. Keynote Speech, ''Neuro-Inspired Adaptive Manycore SoCs and Applications'', International Conference on Control, Automation and Robotics, Nagoya, April 22-24, 2017.

13. Keynote Speech, ''Adaptive SoCs for Smart Autonomous Systems'', 17th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2016), Sousse, December 19-21, 2016.

14. Invited Speech, ''Si-Photonics Technology Towards fJoule/bit Optical Communication in Communication in Many-core Chips,''17th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2014), Sousse, December 19-21, 2014

15. Keynote Speech, AUST International Conference of Technology, Oct. 12-13, 2015. Title: Heterogeneous Systems for Future Computing

16. Invited Speech, 6th International Conference on Soft Computing and Pattern Recognition (SoCPAR2014), August 11-14, 2014.

17. Keynote Speech, IEEE PCSJ 2nd Technical Meeting, Nov. 2, 2013. Title: Towards the Development of a Smart System for Wireless Body Area Networks

18. Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2016

19. Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2015

20. Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2014

21. Invited intensive lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2013

22.  Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2013

23. Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2012

24. Invited v lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2012

25. Invited course, Parallel/Distributed System, Huazhong University of Science and Technology (HUST), Wuhan,  China, 2011

26. Invited intensive lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2011

27. Invited intensive lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2010
    

28. Invited intensive course, Advanced Computer Organization, African University of Science and Technology (Nelson Mandela Institute), Abuja, Nigeria, 2008 -2016 

Invited Lecturer/Professor

• 2024 - present, Invited lecturer, Tokyo University of Foreign Studies, Tokyo, Japan

• 2022 - present, Invited lecturer, Graduate School of Science and Technology, Kyoto Institute of Technology, Japan,

• 2011-2015 Visiting Professor, School of Software Engineering, Huazhong University of Science and Technology, Hong Kong,  China

• 2010-2013 Visiting Professor, Department of Computer Science and Engineering, Hong Kong University of Science and  Technology, China

• 2008-2014 Visiting Professor, Department of Computer Science, African University of Science and Technology (Nelson Mandela's Institute), Abuja, Nigeria

Patents/ 特許

1. 特願2020-094220（特 許第TBC号）Abderazek Ben Abdallah, Khanh N. Dang, "複数のＴＳＶを含むＴＳＶグループが層間を接続するオンチップの３次元 システム''/A three-dimensional system on chip in which a TSV group including a plurality of TSVs provided to connect between layers'', 特願2020-094220 (特許査 定受領日:2024年4月2日)
   

2. 特願 2017-218953（特 許第7239099号）Abderazek Ben Abdallah, Khanh N. Dang, Masayuki Hisada, "3D ネットワークオンチップのための TSV 誤り耐容ルータ装置/A TSV fault-tolerant router system for 3D-Networks-on-Chip," 特願 2017-218953 (2023.03.14)
   

3.  [特 許第6846027 号] (2021.03.03) ベンア ブダ ラ　アブデラゼク (Abderazek Ben Abdallah), ''Defect-tolerant router for network-on-chip'' [ネットワークオンチップ用の欠陥耐性ルータ],特願 2016-100732号 (2016.05.19)
   

4. [特 許第6804072 号] (2020.12.04) ベンアブダラ　ア ブデラゼク (Abderazek Ben Abdallah), 久田雅之, ''Virtual Power Platform Control System [仮想発電所制御システム]'', 特願2020-033678号 (2020.02.28) [.pdf]
   

5. [特 許第6747660号]  (登録日2020.11.08）,  ベンアブダラ　アブデラゼク (Abderazek Ben Abdallah), ''それぞれコ ントロールユニッ トを有す る非ブロック光スイッチを用いる 光ネットワーク・オン・チップシステムのセットアップ方法], 特願2015-196698号 (2015.10.02)
   

6.  [特 許第6284177号]   (登録日2018.2.09）,  ベンアブダラ　アブデラゼク (Abderazek Ben Abdallah), ''誤り耐性ルータ、これを使 用 するＩＣ、及び誤り 耐性ルータの制 御方法'', 特願2013-262523号 (2013.12.19) 

7. Abderazek Ben Abdallah, Khanh N. Dang, Masayuki Hisada, ‘‘Distance-aware Extended Parity Product Coding for multiple faults detection for on-chip links [三次元ICリンクにおける多重故障検出のための距離に基づく拡張パリティ積符号], 特 願 2020-171553
   

8. Abderazek Ben Abdallah, Huankun Huang, Nam Khanh Dang, Jiangning Song, "ＡＩプ ロセッサ," 特願2020-194733 (2020 年11月24日) 

9. Abderazek Ben Abdallah, The H. Vu, Masayuki Hisada, ''Neural Computing Architecture, Fault-tolerant Algorithm, and Design Method for Spiking Neural Networks'', 特願2019-124541 

10. Abderazek Ben Abdallah,Wang Zhishang, Masayuki Hisada, ''An electricity trading system and an electricity trading method [電力取引システム及び電力取引方法に関する], 特願2022-022472 

11. Khanh N. Dang, A. Ben Abdallah, '’Program for generating migration flows for homogeneous computing systems and homogeneous computing devices” [ホ モジニアスコンピューティングシステム及びホモジニアスコ ンピューティングデバイスのマイグレーションフローの生成 プログラム], 特願 2022-196416
    

12.  Abderazek Ben Abdallah,Wang Zhishang, Khanh N. Dang, Masayuki Hisada, ''EV Power Consumption Prediction Method and System for Power Management in Smart Grid [ スマートグリッドにおける電力管理のためのEV消 費電力予測 方法とシステム ]'',   特願2023-020162 

13. Khanh N. Dang, Abderazek Ben Abdallah, Nguyen Ngo Doanh, ''Neural Network Processor [ニュー ラルネットワークプロセッサ],'' 特願2024-047372 (March 22, 2024)
    

14. Abderazek Ben Abdallah , Zhishang Wang, K. N. Dang, Masayuki Hisada, '' Lacquering Robot System [漆塗りロボットシステム],' 特願2024-056380 (Macrh 29, 2023)
    

Books

Authored Books

1. Abderazek Ben Abdallah, Khanh N. Dang (Authors), ''Neuromorphic Computing Principles and Organization,''  Publisher‏: Springer; 2nd Edition, 2024/Q3.

2. Abderazek Ben Abdallah, Khanh N. Dang (Authors), ''Neuromorphic Computing Principles and Organization,''  Publisher‏ : ‎ Springer-Nature; 1st ed. 2022 edition (March 12, 2022), ISBN-10‏ :‎ 3030925242, ISBN-13‏ :‎ 978-3030925246 

3. Abderazek Ben Abdallah (Author), ''Advanced Multicore Systems-on-Chip:Architecture, On-Chip Network, Design,'' Publisher: Springer, 2017, ISBN-13: 978-9811060915, ISBN-10: 98110609162017.

4. Abderazek Ben Abdallah (Author), ''Multicore Systems-on-Chip: Practical Hardware/Software Design,'' 2nd Edition, Publisher: Atlantis-Press, (2013), ISBN-13: 978-9491216916.

Edited Books

1. Abderazek Ben Abdallah, ''Multicore Systems on Chips'', Publisher: Transworld Research Network, ISBN: 978-81-7895-258-1, 2007

Research Projects

1. Dedicated neural network chip for energy management (エネルギーマネージメント向けニューラルネットワークの専用チッ), Collaboration Project with Aizu CSL, Inc. 2023/21 - 2024/1

2. Establishment of federated learning/unlearning technology for large models by utilizing unevenly distributed computational resources (偏在計算資源の活用による巨大モデルに対する連合学習・連合アンラーニング技術の確立), Kakenhi, Fundamental Research (B) (基盤研究(B)（一般）), Ref. 21602-0001, 2024-2027 (Co-Researcher with Peng Li (PI))

3. Development of a Non-invasive Sensory Neuromorphic Prosthesis Hand for Amputees with Touch and Movement Sensations, Competitive Research Funding, CRF-P7, 2022 (PI)

4. Development of Energy-efficient Real-time Heterogeneous Spiking Neuro-inspired System for Deep Neural Networks, Competitive Research Funding, CRF-P5, 2020  (PI)
   

5. Neural network modeling for an energy management system and its implementation on FPGA (エネルギーマネージメント向けニューラルネットワークのモデル構築及び当該ニューラルネットワークのFPGAを用いたチップ化), Fukushima R&D Program (Demonstration Phase) Fund for Renewable Energy Technology (Grant-682), 2020-2021 (Masayuki Hisada, Abderazek Ben Abdallah) 
   

6. Neural network modeling for an energy management system and its implementation on FPGA, Fukushima R&D Program (Demonstration Phase) Fund for Renewable Energy Technology (Grant-682), 2019-2020 (Masayuki Hisada, Abderazek Ben Abdallah)
   

7. Development of Energy-efficient Real-time Heterogeneous Spiking Neuro-inspired System for Deep Neural Networks, Competitive Research Funding, CRF-P5, 2019  (PI)
   

8. Development of Energy-efficient Real-time Heterogeneous Spiking Neuro-inspired System for Deep Neural Networks, Competitive Research Funding, CRF-P3, 2018 (PI)

9. Development of Energy-efficient Real-time Heterogeneous Spiking Neuro-inspired System for Deep Neural Network, Competitive Research Funding, CRF-P2, 2017 (PI)
   

10. Photonic 3D-Network-on-Chip for High-throughput Many-core Systems. P-5-12, Project Achievement: Researched about photonic on-chip communication,Competitive Research Funding, CRF-H26-27 (PI)

11. High-Radix Network-on-Chip Architecture for Future Many-Core Systems. P-37, Project Achievement: Designed in hardware a high-radix network-on-chip architecture and validated its performance with real benchmarks. Registered one patent in Japan about a fault-tolerant 3D router new technology, Competitive Research Funding, H23-25 (PI)
    

12. Embedded Wireless Sensor Network System for Elderly Health Monitoring. P-36, Project Achievement: Designed a wireless body area sensor network system for elderly health monitoring with very promising monitoring accuracy, Competitive Research Funding, H20-22 (PI)
    

13. 3D Printing in Creative Factory Contexts for English Language Learning (Co-investigator), JSPS Kakenhi Research Grant (2015 ~ 2017) – Project number: 30453020 (Co-researcher with Deboprio Roy (PI))

14. Title: A study of fault-tolerant and adaptive routing networks, JSPS Grant-in-Aid for Scientific Research (C), Project Nbr. 15500033 (2003-2005) (Co-reseacher with Y. Tsutomo (PI))

15. Abderazek Ben Abdallah. Title: Functional Assignment Register Microprocessor, the University of Electro-Communications at Tokyo, Ref. UEC XB23, 2002-2004

Awards, Prizes, and Letter of Appreciation   

1. Best Paper Award, 3rd ETLTC2021- ACM Chapter International Conference on Information and Communications Technology", Jan 27-30, 2021.

2. Best Student Paper Award, International Symposium on Ubiquitous Networking 2021 (UNET21), May 19 – May 22, 2021, Marrakesh, Morocco (Virtual due to COVID-19)

3. IEEE International Conference on Big Data and Smart Computing, Kyoto, Japan, 2019

4. ACM Senior Member Award, December 3, 2016

5. IEEE Senior Member Award, February 15, 2014

6. President Prize for Scientific Research and Technology (le prix de président de la République pour la Recherche Scientifique et la technologie, la iournée du savoir), Tunis, Tunisia, July 2010

7. Minister of Higher Education and Research Thank You Letter, from H.E. Lazhar Bououni, Minister of Higher Education and Research in Tunisia, July 29, 2009
   

8. Ambassador of Tunisia in Japan Thank You Letter, from H.E. Noureddine Hached, Ambassador of Tunisia in Japan, September 3, 2009
   

9. Best paper award, 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Fukuoka, Japan, 2010

10. Best presentation award, 19th Intelligent System Symposium (FAN2009), Aizu-Wakamatsu, Japan, Sept. 2009

11. Best paper award, 8th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), Adelaide, Australia, Dec. 3-6, 2007

12. Outstanding achievement Award, Huazhong University of Science and Technology (HUST), Wuhan, China, 1994

13. Outstanding achievement Award, Huazhong University of Science and Technology (HUST), Wuhan, China, 1993

Education

Courses Taught

Current Courses

• Neuromorphic Computing (Graduate level), The University of Aizu, 2022- present

  Computer Architecture, (undergraduate Level), The University of Aizu, 2018 - present

• Introduction to Computer Systems (Undergraduate level), The University of Aizu, 2018 – present

• Introduction to Computer Science and Engineering (Undergraduate level), The University of Aizu, 2022 – present
  

• Parallel Computer Systems (Undergraduate level), The University of Aizu, 2018 – present

Previous Courses

• Advanced Computer Organization (Graduate level, The University of Aizu, 2008 – 2020

• SCCP-001 – Student Cooperative Class Project (System-on-Chip Design), The University of Aizu, 2009-2010

• Computer System Engineering (Undergraduate level), The University of Aizu, 2008-2018

• Embedded Systems (Undergraduate level), The University of Aizu, 2008-2016

• Logic Circuit Design Exercises (Undergraduate level), The University of Aizu, 2008-2018

• Computer Architecture Exercises (Undergraduate level), The University of Aizu, 2008-2018

• Multicore Computing (Graduate level), The University of Aizu, 2010-2015

• Embedded Real-Time Systems (Graduate level), The University of Aizu, 2008 – 2020

• Invited course, Parallel/Distributed System, Huazhong University of Science and Technology (HUST), Wuhan,  China, 2011-2016

• Invited intensive course, Advanced Computer Organization, African University of Science and Technology (Nelson Mandela Institute), Abuja, Nigeria, 2008-2016

• Invited intensive lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2010, 2011, 2012, 2013

Students 

Professional Activities & Service

Memberships of Academic Societies

• Senior member, ACM, Dec. 3, 2016
• Senior Member, IEEE, Feb. 15, 2014
• Member,IEEE computer society Technical committee on computer architecture
• Member, IEEE Computer Society Technical Community on Parallel Processing
• Member, IEEE Circuits and Systems Society
• Member of the European Alliance for Innovation
  
• Member of IEICE

Other Activities

News

Research Related News

• A new patent has been granted. 特願2020-094220（特 許第TBC号）Abderazek Ben Abdallah, Khanh N. Dang, "複数のＴＳＶを含むＴＳＶグループが層間を接続するオンチップの３次元 システム''/A three-dimensional system on chip in which a TSV group including a plurality of TSVs provided to connect between layers'', 特願2020-094220 (特許査 定受領日:2024年4月2日)
• A new patent has been granted. 特許 第7277682号 (May 11, 2023）Abderazek Ben Abdallah, The H. Vu, Masayuki Hisada, 3 次元ネットワークオンチップによるスパイキング ニューラルネットワーク】 ''Spiking Neural Network with 3D Network-on-Chip'', 特願2019-124541 (July 3, 2019)
  
• A new patent has been granted. 特 願2017-218953（特 許第7239099号）Abderazek Ben Abdallah, Khanh N. Dang, Masayuki Hisada, "3D ネットワークオンチップのための TSV 誤り耐容ルータ装置/A TSV fault-tolerant router system for 3D-Networks-on-Chip," 特願 2017-218953 (2023.03.14)
• Local production and consumption model of renewable energy, world's first off-grid energy storage solar carport/ 再 生可能エネルギーの地産地消モデル, 世界初オフグリッド蓄電ソーラーカーポート, 2022.04.01
  
• Mini-lecture on AI-Chip Design, JICA Grassroots Technical Cooperation Project Kickoff Ceremony, January 23, 2023
• Local Production for Local Consumption Model of Renewable Energy, World's first off-grid Energy Storage Solar Carport, Apr 1, 2022   
  
• The press briefing session for the off-grid energy storage solar carport has been uploaded to YouTube/オ フグリッド蓄電ソーラーカーポートのプレス説明会の様子をYouTube にアップしました; (link), Jun 15, 2021     
• Off-grid energy storage solar carport demonstration research begins/オ フグリッド蓄電 ソー ラーカーポート実証研究を開始, May 26, 2021     
• The Savior of a Renewable Energy Society, Fukushima Minpo/ 再 エネ社会 の救世主, 福島民報社, Jan 17, 2021    
  
• 3D-Chip Development, Fukushima Minpo [20181103(9)] Ben Abdallah Laboratory/ ベン・アブデラゼク研究室（コンピュータシステム設計など）3Dチップ開発に力, Nov. 3, 2018     
• President Award/大 統領賞、知識の日;(link), Aug 11, 2010     
• Embedded Multicore Architecture Processing Algorithms for Elderly Monitoring] 効 果的な高齢者モニタリング システムのための組込マルチ コアアーキテクチャによる
   処理アルゴリズム, May 27, 2009

Management and Collaboration Related News

• The School of Computer Science and Engineering at the University of Aizu has been accredited by JABEE March, 1, 2024
• Rencontrer aver le Prof. Slim ABDELKAFI, Directeur de l'ENIS, pour échanger des idées et explorer les opportunités de collaboration entre l'Université d'Aizu et l'ENIS, 23 juin 2023
• Launch of Training Program entitled "Project Model Development of ICT Start-up Human Resource Development for Youth Women'', Tunis, June 19, 2023
• Ceremony Held to Sign the Mamoramdam of Understanding with the University of Carthage, Monday, June 19, 2023
• Interview with Fukushima Minpo, April 2022
  
• The UoA-USM Collaborate to boost E&E sector, Dec. 19, 2022
  
• Invitation of the Ambassador of Tunisia to Japan and a delegation to the University of Aizu, March 30, 2022 [press release]
  
• Interview with the International Cooperation  Career Guide (国際開発キャリアガイド), July 2022
• Meeting with the Minister of Foreign Affairs of Tunisia, June 3, 2022,  Embassy of Tunisia in Japan. (Briefed the Minister about the education system and the advanced research areas at the University of Aizu)  (source).