Educational Resources
Disclaimer:
These technical reports are intended solely for educational
purposes. The use of these reports and any reliance you place on
the information contained within them is strictly at your own
risk.
The reports and writings are authored by Prof. Abderazek Ben
Abdallah and/or his students. Neither the authors nor the
affiliated institutions shall be held liable for any direct,
indirect, incidental, or consequential damages arising from the
use of these reports.
Technical Reports and Tutorials
- PHENIC
Design-Flow Poster, Adaptive Systems Laboratory,
University of Aizu, January 18, 2016
- Introduction
to Network Simulation with OMNET++: A Case of PhoenixSim,
Adaptive Systems Laboratory, University of Aizu, June 1, 2016
- OASIS
3D Fault Tolerant Router Hardware Physical Design with TSVs,
Adaptive Systems Laboratory, University of Aizu, May 28, 2015
- OASIS
3D-Router Hardware Physical Design, Adaptive Systems
Laboratory, University of Aizu, July 8, 2014
- On
the Design of a 3D Network-on-Chip for Many-core SoC,
Adaptive Systems Laboratory, University of Aizu, February 2012
- PHENIC:
Silicon Photonic 3D-Network-on-Chip Architecture, Adaptive
Systems Laboratory, University of Aizu, September 1, 2013
- QSoC:
Implementation of a Simple Queue SoC on FPGA, Adaptive
Systems Laboratory, University of Aizu, January 2009
- BANSMOM
Technical Report, Adaptive Systems Laboratory, University
of Aizu, 2010
- Qasm
– User Friendly Assembler for Queue Computers, Adaptive
Systems Laboratory, University of Aizu, 2010
- Multi-Queue
Core System on a Chip (MQSoC), Adaptive Systems
Laboratory, University of Aizu, 2010
- QC-2
Data Path, Adaptive Systems Laboratory, University of
Aizu, October 2009
- OASIS
3D Fault Tolerant Router Hardware Physical Design (duplicate),
Adaptive Systems Laboratory, University of Aizu, May 28, 2015
- Design
of a 3D Network-on-Chip (duplicate), Adaptive Systems
Laboratory, University of Aizu, February 2012
- QueueCore
– The Strong Wave, Network Computing Laboratory,
University of Electro-Communications, Tokyo, May 2007
- Verilog HDL Quick Guide,
Parallel/Distributed Systems Lab, University of
Electro-Communications, Tokyo, 2004
- QueueCore
Instruction Set Architecture, University of
Electro-Communications, Tokyo, January 2003
- QC-1
Processing Stages Algorithms, University of
Electro-Communications, Tokyo, 2003