Forwarding Unit

Objective:In this lab exercise, you will learn how to design forwarding unit in Verilog and simulate a pipelined datapath with forwarding unit.

Forwarding Unit Specification: Forwarding unit is a hardware solution to deal with data hazards. The idea is to pass proper values early from the pipeline registers to ALU rather than waiting for the WB stage to write the register file. See the Figure 6.38 to get a close-up of the ALU and pipeline register before and after adding forwarding unit. In this design, the only instructions we need to forward are four R-format instructions: add, sub, and, and or. Forwarding unit uses the following conditions to detect two types of hazards:

EX hazard:

if(EX/MEM.RegWrite
and(EX/MEM.RegisterRd != 0)
and(EX/MEM.RegisterRd == ID/EX.RegisterRt))ForwardB = 10

MEM hazard:

if(MEM/WB.RegWrite
and(MEM/WB.RegisterRd != 0)
and(EX/MEM.RegisterRd != ID/EX.RegisterRt)
and(MEM/WB.RegisterRd == ID/EX.RegisterRt))Forward B = 01

Forwarding control will be in the EX stage because the ALU forwarding multiplexors are found in that stage. The values of control signals are shown in Table 1.

Table 1: The control values for the forwarding multiplexors in Figure 6.38. The signed immediate that is another input to the ALU is described in Figure 6.43.
Mux control	Source	Explanation
ForwardA = 00	ID/EX	The first ALU operand comes from the register file.
ForwardA = 10	EX/MEM	The first ALU operand comes from the prior ALU result.
ForwardA = 01	MEM/WB	The first ALU operand comes from data memory or an early ALU result.
ForwardB = 00	ID/EX	The second ALU operand comes from the register file.
ForwardB = 10	EX/MEM	The second ALU operand comes from the prior ALU result.
ForwardB = 01	MEM/WB	The second ALU operand comes from data memory or an early ALU result.

Lab Requirements:

to use Verilog to design forwarding unit described in Forwarding Unit Specification. The inputs are 1-bit EX/MEM.RegWrite, 1-bit MEM/WB.RegWrite, 5-bit EX/MEM.RegisterRd, 5-bit MEM/WB.RegisterRd, 5-bit ID/EX.RegisterRs, and 5-bit ID/EX.RegisterRt. The outputs are 2-bit ForwardA and 2-bit ForwardB.
to add forward unit in the pipelined datapath designed in Lab 6. Figure 6.40 shows you the completed pipelined datapath with forwarding unit. However, the signed-immediate input to the ALU, needed by instructions sw and lw, is missing from Figure 6.40. You have to add a 2:1 multiplexors to select the signed immediate as an ALU input based on Figure 6.43.
to test the pipelined datapath with forwarding unit on the following cases:

Assume registers $1 = D8A3B8D4, $3 = 63B9D6F2, $5 = 0F0F0F0F . To implement the following instruction sequence:

sub

and

add

To store the value in $9 to the data memory using instruction sw, and to print out the result using display task $display. No nop operations (see the explanation of nop operations in Lab 6 are allowed to insert among the instructions sub, and, or, and add.

Assume $1=8, $2=4, $3=7, $4=12, $5=13, $6=19, $7=23, $8=43, $9=56, $10=32, $11=41, $12=4, $13=56, $14=7, $15=5, $16=66. To calculate sum of registers, $1+$2+$3+$4+$5+$6+$7+$8+$9+$10+$11+$12+$13+$14 +$15+$16, using instruction add only, and to store the sum result back to the data memory using instruction sw, and to print out the result using display task $display. No nop operations are allowed to insert between the instruction add.

to write report in English. The report includes the Verilog code of forwarding unit, the schematic of the pipelined datapath with forwarding unit, two stimulus files for test case 1 and 2, and two simulation results. Print out the simulation results in waveform. Mark the simulation results in the waveform figures.

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