| Week 1 | Project 1 : An Example of Verilog Design in Cadence (deadline for the report of Project 1 is the end of exercises on Week 2) |
| Week 2 | Project 2 : Verilog Design of a 32-bit ALU (deadline for the report of Project 2 is the end of exercises on Week 3) |
| Week 3 | Project 3 : Verilog Design of a Register File (deadline for the report of Project 3 is the end of exercises on Week 4) |
| Week 4~6 | Project 4 : Single-Cycle Datapath and Control (deadline for the report of Project 4 is the end of exercises on Week 7) |
| Week 7 | Report Writing for Project 4 |
| Week 8~10 | Project 5 : Pipelined Datapath and Control (deadline for the report of Project 5 is the end of exercises on Week 11) |
| Week 11 | Report Writing for Project 5. |
| Week 12~13 | Project 6 : Forwarding Unit (deadline for the report of Project 6 is the end of exercises on Week 14) |
| Week 14 | Report Writing for Project 6 |
| Week 15 | Q&A for the Final Review |
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