An Example of Verilog Design in Cadence

Objective: In this lab exercise, you will learn the process of Verilog design in Cadence by a simple example. Based on this example, you are required to design a 4-to-1 multiplexor in Verilog and simulate your design in Cadence. Meanwhile, you are also required to read some materials on both Verilog and Cadence. Your knowledge of these two is the key to success of your design tasks in this course.

Lab Requirements:

To learn an example of Verilog design of a 32-bit ALU. Go to an example of Verilog design in Cadence by Prof. Chu. Prof. Chu explained the detail working steps on how to make a Verilog design in Cadence.
To start Cadence, follow the following three steps.
- Login one terminal in hdw1 or hdw2 by inputting your ID and password.
- Launch (login) cadsv gnome-terminal for CAD server. You will be asked to input your password again. Connecting server will be load-balanced. Please select one from 1 of 6 servers, cadsv171-cadsv176.
- Input the command line on the cadsv gnome-terminal: /home/course/logictut/bin/icds&
For the Verilog simulation on Cadence, please follow the three steps described in an example of Verilog design in Cadence by Prof. Chu.
Design a 4-to-1 multiplexor in Verilog using one design styles introduced in Lecture 1. You can use either structural style, or data flow style, or behavioral style, or any mix of them.
- Write your Verilog code for a 4-to-1 multiplexor;
- Write your Verilog stimulus file (testfixture.new) to display all 64 different inputs;
- Simulate your design. Print out your simulation results, write down your name and student number on the printed copy, and hand in the printed copy to the Teaching Assistants or the Instructors.
To learn more about Cadence version 4.4.5, go to User's Guide to Cadence version 4.4.5 or online help.
The following link gives you a very good introduction of Verilog design.
- A Hardware Designer's Guide to Verilog

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