Single-Cycle Datapath and Control

Objective: In this lab exercise, you will use schematic design and Verilog design to implement the single-cycle datapath and control in FIGURE 5.19 (see the figure) in the text book (the index of the figure might be different if you use an old version of the book). All functional units should be designed in Verilog. Only the datapath is designed in schematic. 

Single-Cycle Datapath and Control Specification: Read Section 5.3 of A Simple Implementation in the text book. This simple implementation (see the figure) covers load word (lw), store word (sw), branch equal (beq), the arithmetic-logical instructions add, sub, and, or, set on less than (slt), and immediate instructions addi, andi, ori, and set less than immediate (slti). In this design, every instruction begins execution on one clock edge and completes execution on the next clock edge.

1. Main control unit: The following truth table completely specifies the main control function for the simple single-cycle implementation. The top five rows gives the combinations of input signals  that correspond to the 8 opcodes that determine the control output settings. The bottom portion of the table gives the outputs.

Table 1: Truth table of the main control function for the single-cycle CPU

Input or output	Signal name	R-format	lw	sw	beq	addi	andi	ori	set less than immediate
Inputs	Op5	0	1	1	0	0	0	0	0
	Op4	0	0	0	0	0	0	0	0
	Op3	0	0	1	0	1	1	1	1
	Op2	0	0	0	1	0	1	1	0
	Op1	0	1	1	0	0	0	0	1
	Op0	0	1	1	0	0	0	1	0
Outputs	RegDst	1	0	x	x	0	0	0	0
	ALUSrc	0	1	1	0	1	1	1	1
	MemtoReg	0	1	x	x	0	0	0	0
	RegWrite	1	1	0	0	1	1	1	1
	MemRead	0	1	0	0	0	0	0	0
	MemWrite	0	0	1	0	0	0	0	0
	Branch	0	0	0	1	0	0	0	0
	ALUOp1	1	0	0	0	1	1	1	1
	ALUOp0	0	0	0	1	1	1	1	1

2.  ALU control unit: The following table shows how to set the ALU control inputs based on the 2-bit ALUOp1 and ALUOp0, the 6-bit opcode (op field, bits 31~26), and the 6-bit function code (bits 5~0).

Table 2: ALU control bits

Instruction opcode	ALUOp	Instruction operation	opcode	Function field	Desired ALU Action	ALUcontrol input
LW	00	load word	xxxxxx	xxxxxx	add	010
SW	00	store word	xxxxxx	xxxxxx	add	010
Branch equal	01	branch equal	xxxxxx	xxxxxx	subtract	110
R-type	10	add	xxxxxx	100000	add	010
R-type	10	subtract	xxxxxx	100010	subtract	110
R-type	10	AND	xxxxxx	100100	and	000
R-type	10	OR	xxxxxx	100101	or	001
R-type	10	set less than	xxxxxx	101010	set less than	111
Immediate	11	addi	001000	xxxxxx	add	010
Immediate	11	andi	001100	xxxxxx	and	000
Immediate	11	ori	001101	xxxxxx	or	001
Immediate	11	set less than immediate	001010	xxxxxx	set less than	111

Lab Requirements: Note that all functional units should be designed in Verilog. Only the datapath is created in schematic.

1. to start a datapath design by examining the major elements in the figure, and design each piece one by one in Verilog. Once the major elements are created, you put them together according to the figure in schematic. Note that in order to cope with immediate instructions you should add one more connection bus (5 bits opcode) between Instruction Memory Unit and ALU Control Unit.
1. ALU. Use the ALU you designed in Lab Exercise 1.
2. 32-bit Adder. Modify the ALU Verilog code to create an adder that calculates sum. Note that there are no control lines to Adder.
3. Register file. Use the register file you designed in Lab Exercise 2.
4. Data memory.  There are 65536 32-bit registers in the data memory. Design the data memory based on the register file.
5. Instruction memory. There are 65536 32-bit registers in the instruction memory. Instruction memory has read operation only.
6. Sign-extension unit. It extends the sign bit of the signal to 32-bits.
7. Shift left 2 unit. It shifts the input to the left by 2. It is used for a branch.
8. Multiplexors. A 32-bit wide 2-to-1 multiplexor, and a 5-bit wide 2-to-1 multiplexor.
9. Program counter. A 32-bit register.
2. to design the main control unit in Verilog based on Table 1: Truth table of the main control function for the single-cycle CPU.
3. to design the ALU control unit in Verilog based on Table 2: ALU control bits.
4. to simulate the designed CPU on two stimulus files testfixture.new1 and testfixture.new2.
5. to write report in English. The report must be typed and include
1. the final schematic of the sigle-cycle CPU.
2. Verilog code of each functional unit, including data memeory unit, instruction memory unit, sign-extension unit, shift left 2 unit, 32-bit wide 2-to-1 multiplexor, 5-bit wide 2-to-1 multiplexor, program counter,  the main control unit, and the ALU control unit.
3. simulation results on two stimulus files testfixture.new1 and testfixture.new2.
4. copy of testfixture.new1 with your added comments after each instruction. In the comments, you should manually write down the contents in registers (in Register File) and/or memory cells (in Data Memory) used in each instruction. For example, you could comment the first two instructions like this:

   IMem.cell['h0] ={`LW, 5'd0, 5'd1, 16'h1000}; //lw $1, 'h1000($0) ; Mem.cell['h1000]='h335e; $1 = 'h335e;
   IMem.cell['h4] ={`LW, 5'd0, 5'd2, 16'h1004}; //lw $2, 'h1004($0) ; Mem.cell['h1004]='h0d21; $2 = 'h0d21;

                   
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