Basic Information

Adaptive Systems Laboratory
Professor, Head of the Computer Engineering Division
Web site


Courses - Undergraduate
- Computer Architecture
- Introduction to Computer Systems
- Parallel Computer Systems
Courses - Graduate
- Advanced Computer Organization
- Embedded Real-Time Systems


Computer Systems
Educational Background, Biography
  • 6/1994 B.S., Electrical Engineering, Huazhong University of Science and Technolgy (HUST)
  • 6/1997 M.S., Computer Engineering, Huazhong University of Science and Technology (HUST)
  • 3/2002 Ph.D., Computer Engineering, University of Electro-communications (UEC) at Tokyo
  • 4/2002-3/2007 Research Associate, The University of Electro-Communications (UEC), Tokyo,Japan
  • 4/2007-9/2007 Assistant Professor, The University of Electro-Communications (UEC), Tokyo,Japan
  • 10/2007-3/2011 Assistant Professor, The University of Aizu (UoA), Japan
  • 2010-2013 Visiting Professor, Hong Kong University of Science and Technology (KUST), Hong Kong, China
  • 4/2011-3/2012 Associate Professor, The University of Aizu (UoA), Japan
  • 2011-2015 Visiting Professor, Huazhong University of Science and Technology (HUST), Wuhan,China
  • 4/2012-3/2014 Senior Associate Professor, The University of Aizu (UoA), Japan
  • 4/2014-present Professor, The University of Aizu (UoA), Japan
  • 4/2014-present Head of the Computer Engineering Division, The University of Aizu (UoA), Japan
Current Research Theme
Cognitive Brain-inspired Computing Systems.
Key Topic
Brain-inspired Computing; Spike-based Neural Network Dynamics; Spike-based Learning;
Interconnection Networks; Reliability; Computer Architecture
Affiliated Academic Society
ACM Senior Member, Dec. 3, 2016; IEEE Senior Member, Feb. 15, 2014; Other activities:


Reading and visiting historical places
School days' Dream
To become a school teacher!
Current Dream
Simple is the best!
Favorite Books
" You Can Heal Your Life " 
Messages for Students
Concentration and organization are the keys to your research success.
Publications other than one's areas of specialization

Main research

Cognitive Brain-Inspired Computing Systems

The brain-inspired computing paradigm takes inspiration from the brain to develop energy-efficient circuits and systems for future information processing, capable of highly complicated tasks. Such computing promises to drastically improve critical computational tasks' efficiency, such as decision-making and perception. Unlike the typical artificial neural networks (ANNs), where neurons fire at each propagation cycle, the neurons in a brain-inspired neural networks model, named spiking neural networks (SNNs), fire only when a membrane potential reaches a specific value. Spiking neurons are only activated when sufficient signals are integrated from other neurons, which leads to sparse neural activities at the network level.
In this research, we aim to understand the role of spike-based learning in brain-inspired systems considering various constraints that are not usually taken into account in simulations, such as the effect of variability in the neural network parameters or the impact of bounded weights in the learning/training phase. Our mid-term goal is to develop an innovative cognitive brain-inspired system that can effectively run in parallel with energy efficiency on sequence processing tasks (i.e., a stream of events from sensors), produce intelligent behavior, interact, and adapt to the environment.

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Robust AI Hardware - Neural Network Accelerators & Graph Processing

Deep Neural Networks have shown tremendous progress in many real-world applications (i.e., object recognition, autonomous vehicles, etc.). To improve data processing systems' performance, designers use large-scale models on dedicated hardware platforms such as FPGAs, GPUs, or ASICs. Designers need a long time to collect datasets, train, and design accelerators to keep the trained models private. However, with the growing complexity of DL acceleration, there are severe vulnerabilities in these AI accelerators' hardware implementations. An attacker who does not know the details of structures and designs inside these accelerators can effectively reverse engineer the neural networks by leveraging various side-channel information. Our goal is to study and develop resilient algorithms and hardware for robust trustworthy Edge-AI computing systems for various emerging applications (i.e., Edge, IoT, NoV).

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Reliability and Fault Tolerance

The significant heterogeneity in modern processors/SoCs, which mix many logic layers with memory layers and integrate dozens of processing elements interconnected via a sophisticated complex interconnect, increases the fault's probability in a system. Such a situation is especially relevant for systems working in harsh environments where different kinds of interference may induce several phenomena that can jeopardize the whole system's behavior. The variety of faults are mainly due to cross-talk, electromagnetic interference, the impact of radiations, oxide breakdown, and so on. Therefore, a single failure (corrupted message delivery, time requirements unsatisfactory, etc.) in a module or even a single transistor caused by one of these factors may compromise the entire system's reliability. We research trustworthy hardware and software systems that guarantee several features, such as fault-tolerance, reliability, availability, usability, and security.

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Emerging On-chip/Off-chip Interconnects (si-Photonics, Hybrid, 2D/3D)

The complex integration of semiconductor devices, empowered by emerging interconnect and material innovations, has provided us with tools to connect, analyze, control, and efficiently make decisions. Such complex semiconductor devices/SoCs will contain hundreds of components made of processor cores, DSPs, memory, etc., all interconnected via a novel on-chip interconnect closer to a sophisticated network than current bus-based solutions. This network must provide high throughput and low latency while keeping area and power consumption low. Our research effort is about solving sev eral design challenges to enable such a new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, low-latency adaptive routing. We are also investigating the interconnect scalability challenge in large-scale neuromorphic architectures to develop efficient interconnects that enable complex connections between neurons to incorporate correct spike timing into the design.

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Dissertation and Published Works

A complete list of publications is available here.

Some recent selected publications are included below:

[1] Mark Ogbodo, Khanh N. Dang, Abderazek Ben Abdallah,"On the Design of a Fault-tolerant Scalable Three Dimensional NoC-based Digital Neuromorphic System with On-chip Learning," IEEE Access, 4/2021, DOI: 10.1109/ACCESS.2021.3071089

[2] Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran, "HotCluster: A thermal-aware defect recovery method for Through-Silicon-Vias Towards Reliable 3-D ICs systems," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems March 2021. DOI: 10.1109/TCAD.2021.3069370

[3] Book: Abderazek Ben Abdallah (Author),"Advanced Multicore Systems On-Chip: Architecture, On-Chip Network, Design”, Publishers: Springer; 1st ed, 2017, ISBN-13: 978-9811060915, ISBN-10: 98110609162017.

[4] Z. Wang, M. Ogbodo, H. Huang, C. Qiu, M. Hisada, A. Ben Abdallah, ”AEBIS: AI-Enabled Blockchain-based Electric Vehicle Integration System for Power Management in Smart Grid Platform,” IEEE Access, vol. 8, pp. 226409-226421, 2020, doi:10.1109/ACCESS.2020.3044612.

[5] The H. Vu,Yuichi Okuyama, Abderazek Ben Abdallah, "Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithms and Architecture for 3D-NoC of Spiking Neurons," ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 15, No. 4, Article 34, October 2019. doi: 10.1145/3340963

[6] K. N. Dang, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah,"Scalable design methodology and online algorithm for TSV-cluster defects recovery in highly reliable 3D-NoC systems," IEEE Transactions on Emerging Topics in Computing (TETC), IEEE, Volume 8, Issue 3, pp 577-590, 2020.

[7] K. N. Dang, A. B. Ahmed, A. Ben Abdallah and X. Tran, "TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 672-685, 3/2020. doi: 10.1109/TVLSI.2019.2948878.

[9] Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, "A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue: 11, pp. 3099 – 3112, vol. 2017. DOI: 10.1109/TVLSI.2017.2736004

[10] Khanh N. Dang, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, "Scalable Design Methodology and Online Algorithm for TSV-cluster Defects Recovery in Highly Reliable 3D-NoC Systems," IEEE Transactions on Emerging Topics in Computing, Vol:8, Issue: 3, pp. 577-590, 2020. DOI: 10.1109/TETC.2017.2762407