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How to Set Delay on Circuit Components
Table of Contents
- Add Gate Delay
- Delete Gate Delay
- Simulation with Gate Delay
- Waveform with Gate Delay
1.Add Gate Delay
[1-1]Open schematic
[1-2]Select the gate that you want to set the delay
[1-3]Open Gate Property
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Click Property Icon
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"Edit Object Properties" window is launched
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[1-4]Adding Gate Delay Property
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Click "Add" button on "Edit Object Properties" window
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"Add Property" window is launched
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Input Name(=td), Type(=int), Value(=specified gate delay)
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After input property, Click "OK" button
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Delay setting is finished
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*If you want to apply gate delay on group
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*Please change "Apply to" pull down menu on "Edit Object Properties" window
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2. Delete Gate Delay
[2-1]Select the gate that already set the delay
[2-2]Click property icon. "Edit Object Properties" window is launched
[2-3]Delete Gate Delay Property
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Click "Delete" button on "Edit Object Properties" window
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"Delete Property" window is launched
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Select property which you want to Delete
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After select property, Click "OK" button
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Gate delay is deleted
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3. Simulation with Gate Delay
- Main flow of simulation is same as previous exercise but we have to set a input interval(#time) in test bench very carefully.
- Simple example is as follow
- Critical path(Longest path between input and output) delay of this circuit is 55ns. Therefore the input interval must set larger than 55ns. If the input interval is smaller than 55ns, input signal is changing before output signal is stable.
- Example of test bench file is as follow0(In this example, we set input interval to 60ns)
// Please do not create a module in this file.
// Default verilog stimulus.
initial
begin
a = 1'b0;
b = 1'b0;
cin = 1'b0;
#60
a = 1'b1;
#60
a = 1'b0;
b = 1'b1;
#60
a = 1'b1;
#60
a = 1'b0;
b = 1'b0;
#60
a = 1'b1;
#60
a = 1'b0;
b = 1'b1;
#60
a = 1'b1;
#60
$finish;
end
always #240 cin = ~cin;
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4. Waveform with Gate Delay
- Output signal is stable 55ns after from last input changes. Therefore, we check output signal after this point.
- Simple example is as follow
- Input signal is changed at 60ns. Output signal is stable at 105ns.
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