/* behavioral description of the ALU */
/* the ALU has only three options, logical AND, logical OR,
   and additon. */

`define ALULEN	31
module ALU(Result,ALUOp,A,B,Zero);
    output	[`ALULEN:0] Result;
    reg		[`ALULEN:0] Result;
    output	Zero;
    reg		Zero;
    input	[2:0]	ALUOp;
    input	[`ALULEN:0] A,B;

    always @(A or B or ALUOp)
    begin
        case (ALUOp)
           3'b000: Result  = A & B ;   // AND
           3'b001: Result  = A | B ;   // OR
           3'b010: Result[`ALULEN:0] = A[`ALULEN:0] + B[`ALULEN:0];  // addition
        endcase
        if (Result == 0) Zero = 1;     // Zero detect
        else Zero = 0;
    end

endmodule