RESEARCH

Cognitive Neuromorphic Systems
The neuromorphic computing paradigm promises to drastically improve critical computational tasks' efficiency, such as decision-making and perception. Unlike the typical artificial neural networks (ANNs) where neurons fire at each propagation cycle, the neurons in a neuromorphic neural networks model, named spiking neural network (SNNs), fire only when a membrane potential reaches a specific value. Spiking neurons are only activated when sufficient signals are integrated from other neurons, which leads to sparse neural activities at the network level.
Our first aim is to understand the role of spike-based learning in neuromorphic systems considering various constraints that are not usually taken into account in simulations, such as the effect of variability in the neural network parameters or the impact of bounded weights in the learning/training phase. Our mid-term goal is to develop innovative cognitive neuromorphic systems that can effectively perform sensory-motor tasks, produce intelligent behavior, and interact and adapt to the environment.
Recent Related Publications
The H. Vu,Yuichi Okuyama, Abderazek Ben Abdallah, “Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithms and Architecture for 3D-NoC of Spiking Neurons,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Special Issue on Hardware and Algorithms for Learning On-a-chip for Energy-Constrained On-Chip Machine Learning, Vol. 15, No. 4, Article 34, October 2019. doi: 10.1145/3340963
The H. Vu, Ogbodo Mark Ikechukwu, and Abderazek Ben Abdallah, “Fault-tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems’”, IEEE Access, vol. 7, pp. 90436-90452, 2019.
The H. Vu, Abderazek Ben Abdallah, “Low-Latency K-Means Based Multicast Routing Algorithm and Architecture for Three Dimensional Spiking Neuromorphic Chips”, Big Data and S mart Computing (BigComp) 2019 IEEE International Conference on, pp. 1-8, Kyoto, Fab. 2019, (Best Paper Award Runner-Up)
Abderazek Ben Abdallah, The H. Vu, Masayuki Hisada, ''Neural Computing Architecture, Fault-tolerant Algorithm, and Design Method for Spiking Neural Networks'', 特願2019-093, Patent, JPN (pending)
Related Ongoing Projects (LA)

Deep Neural Network Accelerators
Artificial neural networks have proven to be particularly useful in many audio and visual recognition tasks that are computationally expensive and memory-intensive. Custom hardware-based deep neural network accelerators can surpass their general-purpose processor equivalents in both throughput and energy efficiency. When co-designed with efficient training methods, emerging memory, and scalable interconnects, neural network accelerators transform large and computationally expensive networks into small, sparse, and hardware-friendly alternatives. Our goal is this project is to investigate and develop efficient deep neural networks accelerators based on re-configurable hardware and custom VLSI chips and targeted for emerging Edge/IoT applications.
Recent Related Publications
Yuji Murakami , '' Design of a Neural Network Architecture for Traffic Light Detection Towards Autonomous Driving Vehicles'', Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 3/2019
Ryunosuke Murakami, ''Animal Recognition and Identification with Convolutional Neural Networks for Farm Monitoring,'' Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, 9/2019 
The H. Vu, Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro-inspired Architecture in Hardware, IEEE International Conference on Big Data and Smart Computing  (BigComp 2018), Shanghai, China, January 15-18, 2018.
Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Animal Recognition and Identification with Deep Convolution Neural Networks for Farm Monitoring, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018
Yuji Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”SRAM Based Neural Network System for Traffic-Light Recognition in Autonomous Vehicles, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018
Related Ongoing Projects (LA)

Emerging Interconnects for Network-on-Chips and Neuromorphics
The complex integration of semiconductor devices, empowered by emerging interconnect and material innovations, has provided us with tools to connect, analyze, control, and efficiently make decisions. Such complex semiconductor devices/SoCs will contain hundreds of components made of processor cores, DSPs, memory, etc., all interconnected via a novel on-chip interconnect closer to a sophisticated network than current bus-based solutions. This network must provide high throughput and low latency while keeping area and power consumption low. Our research effort is about solving sev eral design challenges to enable such a new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, low-latency adaptive routing. We are also investigating the interconnect scalability challenge in large-scale neuromorphic architectures to develop efficient interconnects that enable complex connections between neurons to incorporate correct spike timing into the design.
Selected Publications
Nam Khanh Dang, ''Development of On-Chip Communication Fault-Resilient Adaptive Architectures and Algorithms for 3D-IC Technologies,'' Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, September 2017
K. N. Dang, A. B. Ahmed, A. Ben Abdallah and X. Tran, "TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 672-685, 3/2020. doi: 10.1109/TVLSI.2019.2948878.
Khanh N. Dang,  Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”Scalable Design Methodology and Online Algorithm for TSV-cluster Defects Recovery in Highly Reliable 3D-NoC Systems,” IEEE Transactions on Emerging Topics in Computing, 2017 (in press). DOI: 10.1109/TETC.2017.2762407
Achraf  Ben Ahmed, Tsutomu Yoshinaga, Abderazek Ben Abdallah, “Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism,IEEE Transactions on Emerging Topics in Computing, 2017. DOI: 10.1109/TETC.2017.2737016
A. Ben Abdallah, ''A fault-tolerant router, an IC having the same, and a method for controlling the fault tolerant router'' Patent, Japan. Nbr. 6284177 (2018.2.9)

Reliability and Fault Tolerance
The significant heterogeneity in modern processors/SoCs, which mix many logic layers with memory layers and integrate dozens of processing elements interconnected via a sophisticated complex interconnect, increases the fault's probability in a system. Such a situation is especially relevant for systems working in harsh environments where different kinds of interference may induce several phenomena that can jeopardize the whole system's behavior. The variety of faults are mainly due to cross-talk, electromagnetic interference, the impact of radiations, oxide breakdown, and so on. Therefore, a single failure (corrupted message delivery, time requirements unsatisfactory, etc.) in a module or even a single transistor caused by one of these factors may compromise the entire system's reliability. We research trustworthy hardware and software systems that guarantee several features, such as fault-tolerance, reliability, availability, usability, and security. 
Selected Publications
K. N. Dang, A. B. Ahmed, A. Ben Abdallah and X. Tran, "TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 3, pp. 672-685, 3/2020. doi: 10.1109/TVLSI.2019.2948878.
Akram Ben Ahmed, ''High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems,'' Ph.D. Degree, Graduate School of Computer Science and Engineering, University of Aizu, 3/2015.
Akram Ben Ahmed, A. Ben Abdallah,”Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures,Journal of Parallel and Distributed Computing, 74/4 (2014), pp. 2229-2240.
Abderazek Ben Abdallah, N. Dang, Masayuki Hisada, ‘‘Distance-aware Extended Parity Product Coding for multiple faults detection for on-chip links,'' 特願2020-06, JP (pending)
Abderazek Ben Abdallah, Khanh N. Dang, ''A three-dimensional system on chip in which a TSV group including a plurality of TSVs provided to connect between layers'', 特 願 2020-094220, JP (pending)
Adaptive Systems Laboratory
Computer Engineering Division
School of Computer Science and Engineering
The University of Aizu
Aizu-Wakamatsu 965-8580, Japan
Contact:
Abderazek Ben Abdallah
Office phone: 0242-37-2574 (3224)
Email: benab@u-aizu.ac.jp
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