THESES
- Vu
Huy The, ''Algorithms and
Architectures for Spiking Neuromorphic Systems,''
Ph.D. Thesis, Graduate School of Computer Science and
Engineering, The University of Aizu, 9/2019
- Ryunosuke
Murakami, ''Animal Recognition and
Identification with Convolutional Neural Networks
for Farm Monitoring,'' Master's Thesis, Graduate
School of Computer Science and Engineering, The
University of Aizu, 9/2019
- Yuji
Murakami, '' Design of a Neural Network
Architecture for Traffic Light Detection Towards
Autonomous Driving Vehicles,'' Master's Thesis,
Graduate School of Computer Science and Engineering,
The University of Aizu, 3/2019
- Akihito
Kajikawa,''Performance and Complexity Study
of Network-on-Chip with Custom Topology on
FPGA,'' 'Master's Thesis, Graduate School of Computer
Science and Engineering, The University of Aizu,
3/2019
- Shinji
Hironaka, ''Design and Evaluation of a Clustered
LIF Neuro-Core for Spiking Neural Network (NASH),''
Bachelor Thesis, School of Computer Science and
Engineering, The University of Aizu, 3/2019
- Yoshiki
Tanaka, 'Performance Study of Kanji Recognition
with Feed-Forward Neural Network Architecture,''
Bachelor Thesis, School of Computer Science and
Engineering, The University of Aizu, 3/2019
- Nam
Khanh Dang, ”Development of On-Chip
Communication Fault-Resilient Adaptive Architectures
and Algorithms for 3D-IC Technologies”, Ph.D. Thesis,
Graduate School of Computer Science and Engineering,
The University of Aizu, 9/2017.
- Michael
Meyer, ”Micro-ring Fault-resilient
Photonic On-chip Network for Reliable High-performance
Many-core Systems-on-Chip”, Ph.D. Thesis,
Graduate School of Computer Science and Engineering,
The University of Aizu, 3/2017.
- Achraf
Ben Ahmed, ''High-performance, Scalable
Photonics On-chip Network for Many-core
Systems-on-Chip'', Ph.D. Thesis, Graduate School of
Computer Science and Engineering, The University of
Aizu, 3/2016.
- Akram
Ben Ahmed, ''High-throughput Architecture
and Routing Algorithms Towards the Design of Reliable
Mesh-based Many-Core Network-on-Chip Systems'', Ph.D.
Thesis, Graduate School of Computer Science and
Engineering, University of Aizu, 3/2015.
- Masaki
Yamada, ”Performance Study of Character
Recognition with Feed-Forward Neural
Network”, Bachelor Thesis, School of Computer
Science and Engineering, The University of Aizu, March
2018.
- Kanta
Suzuki ”Design of a Leaky, Integrate and Fire
(LIF) Neuron Core for NASH System”, Bachelor
Thesis, School of Computer Science and Engineering,
The University of Aizu, March 2018.
- Kosuke
Takakuwa, ”Study of a Neuro-inspired
Architecture in Hardware”, Bachelor Thesis,
School of Computer Science and Engineering, The
University of Aizu, March 2018.
- Yuji
Murakami, “Design of a Light-Weight Control
Network for High-Bandwidth Photonic Network-on-Chip
Systems”, Bachelor Thesis, School of Computer Science
and Engineering, The University of Aizu, March 2017.
- Nao
Miyamoto, “Video Classification with Numbers of
Detected Trajectories Using Time-space Continuous
Dynamic Programming”, Bachelor Thesis, School of
Computer Science and Engineering, The University of
Aizu, March 2017.
- Kaori
Yatsu, “Visualization of Educational Processor
in UML”, Bachelor Thesis, School of Computer Science
and Engineering, The University of Aizu, March 2017.
- Kajikawa,
Akihito, Evaluation of Error Detection Mechanism
for 3D-OASIS-Network-on-Chip System, Bachelor Thesis,
School of Computer Science and Engineering, The
University of Aizu, March 2016.
- Saito,
Ken, Design, and Analysis of Electrical Control
Router for Hybrid Photonics NoC System, Bachelor
Thesis, School of Computer Science and Engineering,
The University of Aizu, March 2016.
- Okada,
Ryoga, Power and Performance Comparison of
Electronic 2D-NoC and Opto-Electronic 2D-NoC, Bachelor
Thesis, School of Computer Science and Engineering,
The University of Aizu, March 2016.
- Mitsunari
Ishii, Architecture and Design of an Efficient
Router for OASIS 3D Network-on-Chip
System, Bachelor Thesis, School of Computer
Science and Engineering, The University of Aizu, March
2015.
- Yuuki
Tanaka, Design and Evaluation of Efficient
Error Detection Mechanism for OASIS
3D-NoC, Bachelor Thesis, School of Computer
Science and Engineering, The University of Aizu, March
2015.
- Yumiko
Kimezawa, Towards the Design of Dependable
Real-Time System for Remote Health Monitoring of
Elderly People, Master's Thesis, Graduate School
of Computer Science and Engineering, The University of
Aizu, Feb. 2013.
- Achraf
Ben Ahmed, Interactive Real-time Interface
for Smart Remote Health Monitoring and
Analysis, Master's Thesis, Graduate School of
Computer Science and Engineering, The University of
Aizu, Feb. 2013.
- Takayuki
Ochi, A Quantitative Performance Study of
Shared Memory Multicore Systems, Bachelor Thesis,
School of Computer Science and Engineering, The
University of Aizu, Feb. 2013.
- Shuu
Endou, Hardware Prototyping and Evaluation
of Distributed Routing Core Network-Interface for
OASIS NoC Architecture, Bachelor Thesis, School
of Computer Science and Engineering, The University of
Aizu, Feb. 2013.
- Kenichi
Mori, OASIS Network-on-Chip Prototyping on
FPGA, Master's Thesis, Graduate School of
Computer Science and Engineering, The University of
Aizu, Feb. 2012.
- Akram
Ben Ahmed, Architecture and Design of 3D
Network-on-Chip, Master's Thesis, Graduate School
of Computer Science and Engineering, The University of
Aizu, Feb. 2012
- Shohei
Miura, Design of Parametrizable
Network-on-Chip, Master's Thesis, Graduate School
of Computer Science and Engineering, The University of
Aizu, Feb. 2012.
- Ryuya
Okada, Architecture and Design of Core
Network Interface for Distributed Routing in OASIS
NoC, Bachelor Thesis, School of Computer Science
and Engineering, The University of Aizu, Feb. 2012.
- Tomotaka
Kasahara, Performance and Complexity Study
of Multi-QueueCore Systems, Bachelor Thesis,
School of Computer Science and Engineering, The
University of Aizu, Feb. 2012.
- Hiroki
Hoshino, Development of Parallel Queue
Processor Architecture and its Integrated Development
Environment, Master's Thesis, Graduate School of
Computer Science and Engineering, The University of
Aizu, Feb. 2011.
- Taichi
Maekawa, Design and Evaluation of Dual Mode
Processor Architecture, Master's Thesis, Graduate
School of Computer Science and Engineering, The
University of Aizu, Feb. 2011.
- Masashi
Masuda, Produced Order Queue Compiler
Design, Master’s Thesis, Graduate School of
Computer Science and Engineering, The University of
Aizu, Feb. 2011.
- Takahiro
Uesaka, OASIS NoC Topology Optimization
with Short Path Link, Bachelor Thesis, School of
Computer Science and Engineering, the University of
Aizu, Feb. 2011.
- Shunichi
Kato, Shared Memory MultiQueueCore
Processor Design, Bachelor Thesis, School of
Computer Science and Engineering, The University of
Aizu, Feb. 2011, Ref. 10SK-GT10.
- Yumiko
Kimezawa, Multicore SoC Architecture for
Real-time Data Intensive ECG Processing, Bachelor
Thesis, School of Computer Science and Engineering,
the University of Aizu, Feb. 2011.
- Yuuki
Omoto, Development Environment for Single
Chip Computer intended for Queue Computing Development
and Education, Bachelor Thesis, School of
Computer Science and Engineering, The University of
Aizu, Feb. 2010.
- Haga
Yasuyoshi, Architecture and Design of
Application Specific Multicore SoC, Bachelor
Thesis, School of Computer Science and Engineering,
The University of Aizu, Feb. 2010.
- Reo
Honjoya, Development of User-Friendly
Assembler for Queue Computers, Bachelor Thesis,
School of Computer Science and Engineering, The
University of Aizu, Feb. 2010.
- Mori
Kenichi, Optimizations Techniques and FPGA
Prototyping of OASIS Network-on-Chip, Bachelor
Thesis, School of Computer Science and Engineering,
The University of Aizu, Feb. 2010.
- Miura
Shohei, Architecture and Design of
Parameterizable Network-on-Chip, Bachelor Thesis,
School of Computer Science and Engineering, the
University of Aizu, Feb. 2010.
- Masashi
Masuda, Graph Transformation Methods and
Theoretical Performance Evaluation of Queue
Computation Models, Bachelor Thesis, School of
Computer Science and Engineering, The University of
Aizu, Feb. 2009.
- Hiroki
Hoshino, Advanced Hardware Optimization
Algorithms for High-Performance Queue Processor
Architecture, Bachelor Thesis, School of Computer
Science and Engineering, The University of Aizu, Feb.
2009.
- Tachi
Maekawa, Research on Hardware Design of
Dual-Mode Processor Architecture, Bachelor
Thesis, School of Computer Science and Engineering,
the University of Aizu, Feb. 2009.
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