Activities


Refereed Journal Papers
J32
The H. Vu,Yuichi Okuyama, Abderazek Ben Abdallah, “Comprehensive Analytic Performance Assessment and K-means based Multicast Routing Algorithms and Architecture for 3D-NoC of Spiking Neurons,” ACM Journal on Emerging Technologies in Computing Systems (JETC), Special Issue on Hardware and Algorithms for Learning On-a-chip for Energy-Constrained On-Chip Machine Learning, Vol. 15, No. 4, Article 34, October 2019. doi: 10.1145/3340963
J31
Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah and Xuan-Tu Tran, ''TSV-OCT: A scalable online multiple TSV defects localization for 3D-ICs,'' IEEE Transactions on Very Large Scale Integration Systems (to appear) [preprint]
J30
The Vu, Ogbodo Mark Ikechukwu, Abderazek Ben Abdallah, ''Fault-tolerant Spike Routing Algorithm and Architecture for Three Dimensional NoC-Based Neuromorphic Systems'', IEEE Access, Vol 7, pp. 90436-90452, 2019, DOI: 10.1109/ACCESS.2019.2925085
J29
Khanh N. Dang,  Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”Scalable Design Methodology and Online Algorithm for TSV-cluster Defects Recovery in Highly Reliable 3D-NoC Systems,” IEEE Transactions on Emerging Topics in Computing, 2017 (in press). DOI: 10.1109/TETC.2017.2762407
J28
Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue: 11, pp. 3099 – 3112, vol. 2017.  DOI: 10.1109/TVLSI.2017.2736004
J27
The H. Vu, Yuichi Okuyama, Abderazek Ben Abdallah, ‘’Analytical performance assessment and high‑throughput low‑latency spike routing algorithm for spiking neural network systems,’’ The Journal of Supercomputing, 2019, DOI: https://doi.org/10.1007/s11227-019-02792-y
J26
Achraf  Ben Ahmed, Tsutomu Yoshinaga, Abderazek Ben Abdallah, “Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism”, IEEE Transactions on Emerging Topics in Computing, 2017. DOI: 10.1109/TETC.2017.2737016
J25
Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”SAFT-PHENIC: a thermal-aware microring fault-resilient photonic NoC”, The Journal of Supercomputing, Volume 74, Issue 9, pp 4672–4695, 2018. DOI: 10.1007/s11227-018-2463-x
J24
Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Low-overhead Soft-Hard Fault Tolerant Architecture, Design and Management Scheme for Reliable High-performance Many-core 3D-NoC Systems”, Journal of Supercomputing (2017) 73:2705–2729
J23
Achraf Ben Ahmed, A. Ben Abdallah, ''Architecture and Design of Real-Time Systems for Elderly Health Monitoring,'' Journal of Embedded Systems, 2017, Vol.9, No.5, pp.484 – 494,  DOI: 10.1504/IJES.2017.10007717
J22
Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems”, The Journal of Supercomputing, Volume 73, Issue 4, pp 1567–1599 , April 2017. doi: 10.1007/s11227-016-1846-0
J21
Akram Ben Ahmed, Abderazek Ben Abdallah, ”Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC Systems”, Journal of Parallel and Distributed Computing, Volumes 93–94, July 2016, Pages 30-43, ISSN 0743-7315, doi:10.1016/j.jpdc.2016.03.014
J20
Achraf Ben Ahmed, Abderazek Ben Abdallah, “Hybrid Silicon-Photonic Network-on-Chip for Future Generations of High-performance Many-core Systems,” The Journal of Supercomputing, Dec. 2015, Vol. 71, Issue 12, pp 4446-4475. DOI: 10.1007/s11227-015-1539-0
J19
Akram Ben Ahmed, A. Ben Abdallah,”Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures”, Journal of Parallel and Distributed Computing, 74/4 (2014), pp. 2229-2240.
J18
Akram Ben Ahmed, A. Ben Abdallah, ”Architecture and Design of High-throughput, Low-latency and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip”, The Journal  of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532
J17
Abderazek Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, “Natural Instruction Level Parallelism-aware Compiler for High-Performance QueueCore Processor Architecture,” The Journal of Supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.
J16
Abderazek Ben Abdallah, “Efficient Parallel ECG Processing Algorithm and Design of Flexible Health Monitoring System for Elderly People”, Innovation Research Journal, March    2010, pp. 24-27.
J15
Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Compiling for Reduced Bit-Width Queue Processors”, Journal of Signal Processing Systems, Volume 59, Number 1, 45-55, 2010.
J14
Arquimedes Canedo, Abderazek Ben Abdallah,  Masahiro Sowa, “Efficient Compilation for Queue Size-Constrained Queue Processors”, Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.
J13
Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Design and Implementation of a Queue Compiler”, Journal of Microprocessors and Microsystems, Vol. 33, Issue 2, pp. pp. 29-138, 2009.
J12
Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Compiler Support for Code Size Reduction using a Queue-based Processor”, Transactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009.
J11
Abderazek Ben Abdallah, A. Canedo, T. Yoshinaga, M. Sowa, “The QC-2 Parallel Queue Processor Architecture”, Jnl. of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.
J10
Md. Musfiquzzaman Akanda, Abderazek Ben Abdallah, and Masahiro Sowa, “Dual-Execution Mode Processor Architecture,” The Journal of Supercomputing, Vol. 44, No. 2, pp. 103-125, 2008.
J9
A. Acanda, Ben Abdallah, and M. Sowa, “A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model”,  Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007
J8
A. Ben Abdallah, and M. Sowa, “Advanced Power Management Techniques for Mobile Communication Systems”, Journal of Computer Research, Vol. 14, No.2, pp. 109-128, 2007
J7
Nakanishi, A. Canedo, A. Ben Abdallah, and M. Sowa, “Optimizing Reaching Definitions Overhead in Queue Processors”, Journal of Convergence Information technology, 2007, Vol. 2, No. 4, pp. 36-40, 2007
J6
Md. Musfiquzzaman Akanda, A. Ben Abdallah, and M. Sowa, “Dual-Execution Mode Processor Architecture For Embedded Applications”, Journal of Mobile Multimedia, Vol. 3, No.4, Dec. 2007, pp. 347-370.
J5
A. Ben Abdallah, T. Yoshinaga, M. Sowa, “High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core”, The Journal of Supercomputing, Vol. 38, Number 1, pp. 3-15, 2006.
J4
Abderazek Ben Abdallah, Sotaro Kawata, Masahiro Sowa, “Design and Architecture for an Embedded 32-bit Queue Core”, Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.
J3
Viet, T. Yoshinaga, A. Ben Abdallah, and Masahiro Sowa, “Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters”, IPSJ Transactions on Advanced Computing Systems, Vol.46, pp.25-37, Jan. 2005.
J2
M. Sowa, A. Ben Abdallah, and T. Yoshinaga, “Parallel Processor Architecture Based on Produced Order Computation Model”, The Journal of Supercomputing, Vol. 32, No. 3, pp. 217-229, June 2005.
J1
Abderazek Ben Abdallah, Mudar Sarem, Masahiro. Sowa, “Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.
Refereed International Conference Papers
C65
Mark Ogbodo, The Vu, Khanh N. Dang and Abderazek Abdallah, “Light-weight Spiking Neuron Processing Core for Large-scale 3D-NoC based Spiking Neural Network Processing Systems”, The 7th IEEE International Conference on Big Data and Smart Computing, Feb 19, 2020 - Feb 22, 2020,  Pusan, South Korea 
C64
Khanh N. Dang and Abderazek Ben Abdallah “An Efficient Software-Hardware Design Framework for Spiking Neural Network Systems”, 2019 IEEE International Conference on Internet of Things, Embedded Systems and Communications (IINTEC 2019), Tunis, Tunisia, 2019 
C63
Khanh N. Dang, Michael Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, and Xuan-Tu Tran, “2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults”, 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2019), Nov. 11-14, 2019.
C62
Khanh N. Dang, Akram Ben Ahmed, Ben Abdallah Abderazek and Xuan-Tu Tran, “TSV-IaS: Analytic analysis and low-cost non-preemptive on-line detection and correction method for TSV defects'', IEEE Symposium on VLSI (ISVLSI) 2019, pp. 301-306, Jul. 15-17, 2019 .
DOI: 10.1109/ISVLSI.2019.00096
C61 The H. Vu, Abderazek Ben Abdallah, ''A Low-latency K-means based Multicast Routing Algorithm and Architecture for Three Dimensional Spiking Neuromorphic Chips'', IEEE International Conference on Big Data and Smart Computing (BigComp 2019), Kyoto, Japan, Feb 28 - Mar 2, 2019  [Best Paper Award]
C60
The H. Vu, Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro-inspired Architecture in Hardware”, IEEE International Conference on Big Data and Smart Computing  (BigComp 2018), Shanghai, China, January 15-18, 2018.
C59
Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D NoC System”, 25th IEEE Asian Test Symposium (ATS’16), November 21-24, 2016
C58
Khanh N. Dang, Yuichi Okuyama, Abderazek Ben Abdallah, ”Soft-Error Resilient Network-on-Chip for Safety-Critical Applications”, 2016 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), June 27 – 29, 2016
C57
Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, “A Soft-Error Resilient 3D Network-on-Chip Router for Highly-reliable Multi-core Systems”, IEEE 7th International Conference on Awareness Science and Technology (iCAST 2015), Sep. 22-24, 2015.
C56
Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Hybrid Photonic NoC based on Non-blocking Photonic Switch and Light-weight Electronic Router”, Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015.
C55
Michael Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Optical Router for Reliable Network-on-Chip Systems”, Proc. of 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs (MCSoC-15), Sept. 2015.
C54
Michael Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Fault-tolerant Photonic Network-on-Chip,” Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015.
C53
Achraf Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah,”Non-blocking Electro-optic Network-on-Chip Router for High-throughput and Low-power Many-core Systems”,  Proc. of the World Congress on Information Technology and Computer Applications 2015, June 11-13, 2015
C52
Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah,”Efficient Router Architecture, Design and Performance Exploration for Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC)”, Proc. Of the International Conference on Information Science and Control Engineering, 04/2015.
C51
Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, ”Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems”, IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Manycore SoCs (MCSoC-14), pp. 197-2014, Sept. 2014.
C50
Achraf Ben Ahmed, A. Ben Abdallah, ”PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-throughput Many-core Systems-on-Chip”, IEEE Proceedings of the 14th International Conference on Sciences and Techniques of Automatic control and computer engineering, 2013
C49
Akram Ben Ahmed, A. Ben Abdallah, ”Fault-tolerant Routing Algorithm with Deadlock Recovery Support for 3D-NoC Architectures”, IEEE Proceedings of the 7th International Symposium on Embedded Multicore SoCs, Sept. 2013
C48
Achraf Ben Ahmed, A. Ben Abdallah, ”Hardware/Software Prototyping of Dependable Real-Time System for Elderly Health Monitoring”, IEEE Proc. of the World Congress on Computer and IT, ICMAES, June 2013.
C47
Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ”Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era”, Proc. IEEE 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013′), July 2013.
C46
Akram Ben Ahmed, A. Ben Abdallah, ”Low-overhead Routing Algorithm for 3D Network-on-Chip”, IEEE Proc. of The Third International Conference on Networking and Computing (ICNC’12), pp. 23-32, 2012.
C45
Akram Ben Ahmed, A. Ben Abdallah, ”LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture”, IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012.
C44
Achraf Ben Ahmed, Yumiko Kimezawa, A. Ben Abdallah, ”Towards Smart Health Monitoring System for Elderly People”, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 248-253, 2012.
C43
Akram Ben Ahmed, A. Ben Abdallah, ”ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications”, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012.
C42
A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, ”Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture”, The Journal of Supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.
C41
A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, ”Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoCs”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010. [Best Paper Award]
C40
K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ”Advanced Design Issues for OASIS Network-on-Chip Architecture”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.
C39
A. Ben Abdallah, Y. Haga, K. Kuroda, ”An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records”, IEEE Proc. of the 39th the International Conference on Parallel Processing Workshop, San Diego, pp.99-103, Sept. 13-16, 2010.
C38
M. Masuda, A. Ben Abdallah, A. Canedo, ”Software and Hardware Design Issues for Low-Complexity High-Performance Processor Architecture”, IEEE ICPPW’09 Proc. of the 2009 International Conference on Parallel Processing Workshops, pp. 558-565, 2009.
C37
Y. Haga, A. Ben Abdallah, and K. Kuroda, ”Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing”, The 19th Intelligent System Symposium (FAN 2009), pp.298-303, Sep. 2009.
C36
S. Miura, A. Ben Abdallah, and K. Kuroda, ”PNoC – Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration”, The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep. 2009.
C35
K. Mori, A. Ben Abdallah, and K. Kuroda, ”Design and Evaluation of a Complexity-Effective Network-on-Chip Architecture on FPGA”, The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009.
C34
M. Masuda, A. Canedo, A. Ben Abdallah, ”Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture”, The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009. (Best Presentation Award).
C33
T. Maekawa, A. Ben Abdallah, and K. Kuroda, ”Single Instruction Dual-Execution Model Processor Architecture”, Proc. IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008), pp.30-36, Dec. 2008.
C32
H. Hoshino, A. Ben Abdallah, and K. Kuroda, ”Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model”, IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.
C31
A. Canedo, A. Ben Abdallah, and M. Sowa, ”Quantitative Evaluation of Common Sub-expression Elimination on Queue Machines”, Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.
C30
Arquimedes Canedo, Ben Abdallah Abderazek, Masahiro Sowa, ''New Code Generation Algorithm for QueueCore - An Embedded Processor with High ILP,'' 8th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), Adelaide, Australia, Dec. 3-6, 2007 (Best Paper Award).
C29
A. Ben Abdallah, T Yoshinaga, and M. Sowa, ”Mathematical Model for Multiobjective Synthesis of NoC Architectures”, IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 2007.
C28
A. Canedo, A. Ben Abdallah, and M. Sowa, ”Queue Register File Optimization Algorithm for QueueCore Processor”, Proc. IEEE 19th International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.
C27
A. Canedo, A. Ben Abdallah, and M. Sowa, ”An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model”, Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007
C26
A. Canedo, A. Ben Abdallah, and M. Sowa, ”Compiler Framework for an Embedded 32-bit Queue Processor”, Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.
C25
A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Scalable Core-Based Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC (MCSoC)”, Proc. IEEE 35th International Conference on Parallel Processing Workshops, Aug. 14-18th, pp. 345-352, 2006.
C24
A. Ben Abdallah, Masahiro Sowa, ”Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization”, Proc. of the Joint Symposium on Science, Society and Technology (JASSST2006), pp. 1-7, Dec. 4-9th, 2006.
C23
A. Ben Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core”, Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005.
C22
M. Akanda, A. Ben Abdallah, S. Kawata, and M. Sowa, ”An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture”, Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 77-86, Dec. 2005.
C21
A. Markovskij, A. Ben Abdallah, S. Kawata, and M. Sowa, ”Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation”, Proc. of the 38th International Symposium on Microarchitecture (MICRO-38), Nov. 2005.
C20
Ta Quo Viet, T. Yoshinaga, and A Ben Abdallah, ”Performance Enhancement for Matrix Multiplication on an SMP PC Cluster”, Summer United Workshops on Parallel, Distributed and Cooperative Processing, August 2005.
C19
A. Ben Abdallah, Markov Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme”, Proc. IEEE of the 7th High-Performance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
C18
Shigeta, L.-Q. Wang, N. Yagishita, A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”QJava: Integrate Queue Computational Model into Java”, Proc. of the Joint Japan-Tunisia Workshop on Computer Systems and Information Technology (JT-CSIT’04), July 2004.
C17
A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, ”Design of Producer-Order Parallel Queue Processor Architecture”, Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.
C16
M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”High-performance Hybrid Processor Architecture with Efficient Hardware Usability”, Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.
C15
H. Sasaki, Y. Okumura, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Theoretical Evaluation of Simultaneous Multi-threading Parallel Queue Processor Architecture”, Proc. International Conference on Circuits/Systems, Computers and Communications, July 2004.
C14
A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”On the Design of a Register Queue-Based Processor Architecture (FaRM-rq)”, Proc. of the International Symposium of Parallel and Distributed Processing and Applications (ISPA 2003), pp.248-262, July 2003.
C13
L. Q. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java Bytecode”, Proc. of International Technical Conference in Circuits/Systems, Computers and Communications (ITC-CSCC2003), pp. 900-903, July 2003.
C12
Tao. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPP”, SACSIS03, pp.299-306, 2003.
C11
T. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPs”, Proc. of Symposium on Advanced Computing Systems and Infrastructures, pp.299-306, 2003.
C10
A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Complexity Analysis of a Functional Assignment Register Microprocessor”, Proc. of the Int. Workshop on Modern Science and Technology (IWMST02), pp.116-123, Sep. 2002.
C9
A. Ben Abdallah, Mudar Sarem, and M. Sowa, ”Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.
C8
Ben Abdallah, Mudar Sarem, and M. Sowa, ”Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.
C7
A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARM-Queue Mode: On a Practical Queue Execution Model”, Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, pp.939-944, July 2001.C
C6
Kiriuka Nikolova, A. Ben Abdallah, and M. Sowa, ”Dynamical Critical Path Parallelism-Independent Scheduling Algorithm for Distributed Computing Systems”, Proc. of the International Technical Conference on Circuits and Systems, Computers and Communications, pp. 929-934, July 2001.
C5
A. Ben Abdallah, and M. Sowa, ”DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor”, Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT’99), pp.131-136, October 1999.
C4
A. Ben Abdallah, M. Sarem, and M. Sowa, ”A Survey on the advances of Disc I/O performance metrics”, Proc. of International Conference on Robotics, Vision and Parallel Processing, pp. 522-527, July 1999.
C3
A. Ben Abdallah, A. Kazi, and L. L. Shan, ”Multi-Function Interface Board for Teaching Topics and Development System”, APST97, Yata, PRC. Pp.134-139, Sep. 1997
C2
A. Ben Abdallah, A. Kazi, and L. L. Shan, ”Multi-Function Interface Board for Teaching Topics and Development System”, APST97, Yata, PRC. Pp.134-139, Sep. 1997
C1
L. L. Shan, L. Liu, and A. Ben Abdallah, ”The Master-Slave Two Level Distributed Microcomputer Measuring and Monitoring System”, ISMTIT, Japan, pp. 161-164, 1996
Domestic Conference Papers
DC15
Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Animal Recognition and Identification with Deep Convolutional Neural Networks for Farm Monitoring”, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018
DC14
Yuji Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”SRAM Based Neural Network System for Traffic-Light Recognition in Autonomous Vehicles”, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018
DC13
Kanta Suzuki, Yuichi Okuyama, Abderazek Ben Abdallah, ”Hardware Design of a Leaky Integrate and Fire Neuron Core Towards the Design of a Low-power Neuro-inspired Spike-based Multicore SoC”, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018
DC12
A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing”, Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.
DC11
A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, ”PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL”, Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.
DC10
T. Viet, T. Toshinga, A. Ben Abdallah, and M. Sowa, ”Optimization for Hybrid MPI-OpenMP Programs on a Cluster of SMPs”, SACSIS 2004.
DC9
A. Musfiquzzaman, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Computation Mechanism For Parallel Execution in Parallel Queue Processor”, Proc. of Information Processing Society of Japan, Vol. 60, pp. 3F-4, 2004.
DC8
A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)”, Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.
DC7
L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Fast, Effective Instruction Generation Algorithm For Queue-Java Compiler (QJAVAC)”, Proc. of Information Processing Society of Japan, Vol.2003, No.40, pp.55-60, 2003.
DC6
L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”An Ambiguous Context-Free Grammar for Deterministic Parsing In Queue-Java Compiler”, Proc. of Information Processing Society of Japan, Vol.2003, No.62, pp.7-12, 2003.
DC5
L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java”, Proc. of IIEICE Technical Conference, 2003.
DC4
A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, ”FARM QUEUE MODE: On a Practical Queue Execution Model (QEM)”, TIWSS’01, October 2001.”’
DC3
A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARM-Queue Execution Model: Towards an Alternative Computing Paradigm”, Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000.
DC2
A. Ben Abdallah, M. Sarem., and M. Sowa, ”Acyclic DFG on a Queue Machine”, Proc. of JSPP, Tokyo, pp.119-120, 2000.
DC1
A. Ben Abdallah, and M. Sarem, ”Instruction Scheduling System for Superscalar Processor”, JSPP, Tokyo, pp.161, Apr. 2000.
Patents
P5
Abderazek Ben Abdallah, The H. Vu, Masayuki Hisada, ''Neural Computing Architecture, Fault-tolerant Algorithm, and Design Method for Spiking Neural Networks'',整理番号2019093
P4
Abderazek Ben Abdallah, ''A fault-tolerant router, an IC having the same, and a method for controlling the fault tolerant router'', Nbr 2013-262523, Japan
P3
Abderazek Ben Abdallah, Khanh N. Dang, Masayuki Hisada, A TSV fault-tolerant router system for 3D-Networks-on-Chip, 特願 2017-218953, Japan.
P2
Abderazek Ben Abdallah, Methods, Algorithm, and Robust Fault-tolerant Router for Reliable Networks-on-Chip,特願 2016-100732, Japan
P1
Abderazek Ben Abdallah, A Photonic Network-on-Chip System employing non-blocking photonic switches with respective control units, and a method of setting up the Photonic Network-on-Chip, 特願2015-196698, Japan
Books
B4
B3
B2
B1
B0
Abderazek Ben Abdallah (Author), '' Neuromorphic Computing Principles and Organization'', Publisher: Springer Nature (to be released)
Abderazek Ben Abdallah (Author), ''Advanced Multicore Systems-on-Chip:Architecture, On-Chip Network, Design'', Publisher: Springer, 2017, ISBN-13: 978-9811060915, ISBN-10: 98110609162017.
Abderazek Ben Abdallah (Author), ''Multicore Systems-on-Chip: Practical Hardware/Software Design,'', 2nd Edition, Publisher: Atlantis-Press, (2013), ISBN-13: 978-9491216916.
Abderazek Ben Abdallah (Author), ''Multicore Systems-On-Chip: Practical Hardware/Software Design,'' 1st Edition, Publisher: Atlantis-Press, 2010, ISBN 978-90-78677-22-2.
Abderazek Ben Abdallah (Editor & one of the Authors), ''Multicore Systems on Chip'', Publisher: Signpost, 2007, ISBN:978-81-7895-258-1
Awards
A7
Best paper runner up award, IEEE International Conference on Big Data and Smart Computing, Kyoto, Japan, 2019
A6
ACM Senior Member Award, December 3, 2016
A5
IEEE Senior Member Award, February 15, 2014
A4
Best paper award, 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Fukuoka, Japan, 2010
A3
President Prize for Scientific Research and Technology (TKD), Tunis, Tunisia, July 2010
A2
Best presentation award, 19th Intelligent System Symposium (FAN2009), Aizu-Wakamatsu, Japan (with my student), Sept. 2009 (with student)
A1
Best paper award, 8th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), Adelaide, Australia, Dec. 3-6, 2007 (with student)
Invited Talks, Courses
ITC26 Invited Speaker, ''Neuromorphic Computing: Beyond-CMOS Approach to Future Computing'', IRE2020, Osaka, Japan, April 2020.
ITC25 Invited talk, ''Energy Management System based on High-speed, Low-power AI-Chip, and Electrical Vehicles (EVs)'', Third Symposium on AI Center will be held on Saturday, Universoty of Aizu, Aizu-Wakamatsu, November 23, 2019.
ITC24 Keynote Speaker , ''The Future of Machine Learning: Neuromorphic Chips,'' ACM 5th International Conference of Computing for Engineering and Sciences, Hammamet, 20-22 July 2019
ITC23 Invited Speaker, ''Neuromorphic Computing Chips for AI at the Edge'', Machine Learning and Data Analytics Symposium (MLDAS 2019), March 1-2, Doha, 2019 (slides.pdf)
ITC2 Keynote Speaker, ''Artificial Intelligence Chips for Intelligent Systems'', 2019 International Conference on Intelligent Autonomous Systems (ICoIAS’2019), Singapore, 2019
ITC21 Invited Talk, ''Artificial Intelligence Chips: From Data Centers to Edge and IoT Computing'', 2nd Symposium on AI Center, The University of Aizu, December 8, 2018.(slides.pdf)
ITC20 Keynote Speech, ''Neuro-inspired Computing Systems & Applications'', 2018 International Conference on Intelligent Autonomous Systems (ICoIAS’2018), Singapore, March 1-3, 2018 (slides.pdf)
ITC19 Invited Talk, ''Developing a Mindset for Innovation & Entrepreneurship'', 1st ACM Chapter Networking Seminar on Globalization & Innovative Thinking, 2017/11/26, University of Aizu
ITC18 Keynote Speech, ''Neuro-Inspired Adaptive Manycore SoCs and Applications'', International Conference on Control, Automation and Robotics, Nagoya, April 22-24, 2017.
ITC17 Keynote Speech, ''Adaptive SoCs for Smart Autonomous Systems'', 17th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2016), Sousse, December 19-21, 2016.
ITC16 Keynote Speech, ''Adaptive SoCs for Smart Autonomous Systems'', 17th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2016), Sousse, December 19-21, 2016.
ITC15 Invited Speech, ''Si-Photonics Technology Towards fJoule/bit Optical Communication in Communication in Many-core Chips,''17th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2014), Sousse, December 19-21, 2014.IT3 (slides.pdf)
ITC14 Keynote Speech, AUST International Conference of Technology, Oct. 12-13, 2015. Title: Heterogeneous Systems for Future Computing
ITC13 Invited Speech, 6th International Conference on Soft Computing and Pattern Recognition (SoCPAR2014), August 11-14, 2014.
ITC12 Keynote Speech, IEEE PCSJ 2nd Technical Meeting, Nov. 2, 2013. Title: Towards the Development of a Smart System for Wireless Body Area Networks”.
ITC01 Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2016
ITC10 Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2015
ITC9 Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2014
ITC8 Invited lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2013
ITC7 Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2013
ITC6 Invited course, Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2012
ITC5 Invited lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2012
ITC4 Invited course, Parallel/Distributed System, Huazhong University of Science and Technology (HUST), Wuhan,  China, 2011
ITC3 Invited lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2011
ITC2 Invited lectures, Network-on-Chip, Hong Kong University of Science and Technology (KUST), Hong Kong, China, 2010
ITC1
Invited Course, Logic and Computer Systems, African University if Science and Technology, Abuja, Nigeria, 2008
Academic and Social Activities
Editorial and Councils Involvement
2014-
Guest Editor, IEEE Transactions on Emerging Topics in Computing, Special Issue on Parallel Programming and Architecture Support for Many-core Embedded Systems, 2014.
2015-
Associate Editor, Journal of Embedded Systems, Inner Science, 2015 – present
2013-
Editor, Journal of Embedded Systems, Inner Science, 2013-2015
2013
Guest Editor, Special Issue on Embedded Multicore and Many-core Architectures, Journal of Embedded Systems (IJES), InderScience, 2013.
2013
Editor, Journal of Adaptive and Innovative Systems, InderScience, 2013-present.
2007-
Editor, Advances in Next Generation Mobile Multimedia, Book Series, 2007-2009
2007
Editor, Journal of Mobile Computing and Multimedia Communications (IJMCMC), 2007
2008
Editor, Journal of Convergence Information Technology, 2008-2010.
2009
Member of the Governmental High-Level Committee for Science and Technology, Tunisia (2009-2011)
2008
Director, the Support Association for International Students of the University of Aizu (SAISUA), Aizu-Wakamatsu, Japan, 2008-2011
2002-
Reviewer (past & present): Journal of Parallel and Distributed Computing; IEEE Computer; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; IEEE Micro; IEEE Network Magazine; IET Journal of Circuits, Devices & Systems;  Journal of Parallel Computing; Journal of Supercomputing; IEICE Transactions; Integration: The VLSI Journal; ACM Journal on Emerging Technologies in Computing Systems.
Memberships of Academic Societies
2016
Senior Member of ACM (Association for Computing Machinery)
2014
Senior Member of IEEE (Institute of Electrical and Electronics Engineers)
2018
Member of the IEEE Technical Committee on Parallel Processing
2018
Member of the IEEE Society Technical Committee on Computer Architecture
2012
IEEE Computer Society Technical Committee on Microprocessors and Microcomputers
2012
Member of  IEICE (The Institute of Electronics, Information, and Communication Engineers)
Involvement in Conference and Research Meetings
2004-
Founder and Steering Chair of the IEEE Symposium on Embedded Multicore/Manycore Systems-on-chip (MCSoC) Series, 2004 – present
2010-
Program member of the IEEE Symposium on Low-Power and High-Speed Chips (COOLChips), Yokohama, 2010 – present
2012
Program Co-chair, 5th International Workshop of Engineering Parallel and Multicore Systems, July 4-6, 2012, Palermo, Italy.
2009
Publication Chair, 4th International Conference on Frontier of Computer Science and Technology (FCST2009), Shanghai, 2009.
2009
Program Chair, IEEE International Conference on Embedded Software and Systems, Hangzhou, Zhejiang, China, 2009.
2007
General Chair, 3rd International Workshop on Embedded Single and Multicore Systems on Chips, In conjunction with 36th ICPP-2007, China, 2007
2206
Steering Chair, 2nd International Workshop on SoC and MCSoC Design with MoMM 2006, Yogyakarta, Indonesia, 2006.
2006
General Co-chair, 8th International Workshop on High-Performance Scientific and Engineering Computing, Columbus, Ohio, USA, August 18, 2006
2005
Program Co-chair, International Conference on Computer design, CDES-05, Las Vegas, 2005.
2004
Program Chair, Joint Japan-Tunisia Workshop on Computer Systems and Information Technology (JT-CSIT2004), The University of Electro-Communications, Tokyo, Japan, 2004.
2002
TPC member for +30 International conferences and workshops

Updated on 11/18/2019, (c) ABA