Basic Information

Affiliation
Adaptive Systems Laboratory
Title
Professor, Head of the Computer Engineering Division
E-Mail
benab@u-aizu.ac.jp
Web site
http://adaptive.u-aizu.ac.jp/?page_id=808

Education

Courses - Undergraduate
- Introduction to Computer Systems
- Parallel Computer Systems
Courses - Graduate
- Advanced Computer Organization
- Embedded Real-Time Systems
- Parallel and Distributed Computing

Research

Specialization
Fault-tolerance and Robustness; Emerging Interconnect Technologies for Multi-core Architectures;
Neuro-inspired Architectures/Chips; AI and Machine Learning Systems; Ultra-low power Embedded and Multicore SoCs
Educational Background, Biography
Career 
  • 2002.4  Research Associate, the University of Electro-Communications at Tokyo (UEC)
  • 2007.10 Assistant Professor, the University of Aizu (UoA)
  • 2011.4  Associate Professor, the University of Aizu (UoA)
  • 2011/3, 2012/3, 2013/3, 2014/3, 2015/3 Visiting Professor, Huazhong University of Science and Technology (HUST)
  • 2012.4  Senior Associate Professor, the University of Aizu (UoA)
  • 2010/3, 2011/3, 2012/3, 2013/3 Visiting Professor, Hong Kong University of Science and Technology (KUST)
  • 2014.4  Professor, the University of Aizu (UoA) 
  • 2014.4  Head of the Division of Computer Engineering, the University of Aizu (UoA) 
Education
  • 1994.6 BEng, Huazhong University of Science and Technology (HUST)
  • 1997.6 MEng, Huazhong University of Science and Technology (HUST)
  • 2002.3 Ph.D., the University of Electro-Communications Tokyo (UEC)
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Current Research Theme
Neuro-Inspired Architecture/Chip with Fault-tolerant Scalable Interconnect for Learning in Networks of Spiking Neurons
Key Topic
-Fault-tolerance and Robustness ( self-healing, failure prediction, error preemption, and recovery algorithms)
-Emerging Interconnect Technologies for Multi-core Architectures (photonics, Si-photonics, Hybrid, 3D architecture implementation)
-Neuro-inspired Architectures/Chips
-AI and Machine Learning Systems
-Ultra-low power Embedded and Multicore SoCs
Affiliated Academic Society
-Senior member of IEEE, -Senior member of ACM -Member of IEICE

Others

Hobbies
Reading and visiting historical places
School days' Dream
To become a school teacher!
Current Dream
Achieve outstanding research results that can benefit the whole humanity.
Motto
Simple is the best!
Favorite Books
" You Can Heal Your Life ". 
Messages for Students
Concentration and organization are the keys to your research success.
Publications other than one's areas of specialization

Main research

Cognitive Neural Networks Hardware Accelerators and Chips for Emerging AI Applications

In recent years, neuroscience research has revealed a great deal about the structure and operation of individual neurons, and medical tools have also revealed a great deal about how neural activity in the different regions of the brain follows a sensory stimulus. Moreover, the advances of software-based Artificial Intelligence (AI) have brought us to the edge of building brain-like functioning devices and systems overcoming the bottleneck of the conventional von Neumann computing style. The neuro-inspired technology based on spiking neural network (SNN) is one of the efficient solutions for brain-inspired cognitive computing in both learning and inference tasks. Hardware implementations of spiking neural network systems are power-efficient and effective methods to provide cognitive functions on a chip compared with the conventional stored-program computing style. Energy-efficient devises/accelerators for neural-networks are needed for power-constrained devices, such as smartphones, drones, robots, and autonomous-driving cars. We are investigating energy-efficient devices and accelerators for NNs on FPGA and ASIC. We are also investigating how to map the latest deep learning algorithms to application-specific hardware and emerging devices/systems to achieve orders of magnitude improvement in performance and energy efficiency.

View this research

Dissertation and Published Works

[1] Book: Abderazek Ben Abdallah (Author), ”Advanced Multicore Systems On-Chip: Architecture, On-Chip Network, Design”, Publishers: Springer; 1st ed, 2017, ISBN-13: 978-9811060915, ISBN-10: 98110609162017.

[2] Khanh N. Dang, Akram Ben Ahmed, Yuichi Okuyama, and Abderazek Ben Abdallah, ”Scalable Design Methodology and Online Algorithm for TSV-cluster Defects Recovery in Highly Reliable 3D-NoC Systems”, IEEE Transactions on Emerging Topics in Computing, 2017 (in press). DOI: 10.1109/TETC.2017.2762407.

[3] Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue: 11, pp. 3099 – 3112, Nov. 2017. DOI:10.1109/TVLSI.2017.2736004.

[4] Achraf Ben Ahmed, Tsutomu Yoshinaga, Abderazek Ben Abdallah, “Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism”, IEEE Transactions on Emerging Topics in Computing, 2017 (in press). DOI: 10.1109/TETC.2017.2737016

[5] A. Ben Abdallah, A. Canedo, T. Yoshinaga, and M. Sowa, The QC-2 Parallel Queue Processor Architecture”, Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.

Complete list of publications: http://adaptive.u-aizu.ac.jp/?page_id=739