Basic Information

Adaptive Systems Laboratory
Professor, Head of the Computer Engineering Division
Web site


Courses - Undergraduate
-Computer System Engineering-Embedded Systems
Courses - Graduate
Advanced Computer Organization,Embedded Real-Time Systems,Multicore Computing,Distributed Computing.


Computer Systems, Adaptive Systems.
Educational Background, Biography
  • 2002.4  Research Associate, the University of Electro-Communications at Tokyo (UEC)
  • 2007.10 Assistant Professor, the University of Aizu (UoA)
  • 2011.4  Associate Professor, the University of Aizu (UoA)
  • 2011/3, 2012/3, 2013/3, 2014/3, 2015/3 Visiting Professor, Huazhong University of Science and Technology (HUST)
  • 2012.4  Senior Associate Professor, the University of Aizu (UoA)
  • 2010/3, 2011/3, 2012/3, 2013/3 Visiting Professor, Hong Kong University of Science and Technology (KUST)
  • 2014.4  Professor, the University of Aizu (UoA) 
  • 2014.4  Head of the Division of Computer Engineering, the University of Aizu (UoA) 
  • 1994.6 B.S. Degree, Huazhong University of Science and Technology (HUST)
  • 1997.6 M.S. Degree, Huazhong University of Science and Technology (HUST)
  • 2002.3 Ph.D. Degree, the University of Electro-Communications at Tokyo (UEC)
Current Research Theme
Adaptive Neuro-inspired Computing System and Platform for Complex Cognition Tasks
Key Topic
Adaptive and reconfigurable multi/manycore and processor architectures; photonic interconnects; on-chip networks; power- and reliability-aware computing; neuro-inspired computing; High-performance Computing
Affiliated Academic Society
-Senior member of IEEE, <br>-Senior member of ACM<br>-Member of IEICE


Reading and visiting historical places
School days' Dream
To become a school teacher!
Current Dream
Achieve outstanding research results that can benefit the whole humanity.
Simple is the best!
Favorite Books
" You Can Heal Your Life ". 
Messages for Students
Concentration and organization are the keys to your research success.
Publications other than one's areas of specialization

Main research

Research on Adaptive Neuro-inspired Computing System and Platform

The biological brain implements massively parallel computations using a complex architecture that is different from the conventional Von Neumann computing style. Our brain is a low-power, fault-tolerant and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died. Our goal in this project is to research and develop an adaptive and reliable neuro-inspired system and platform with on-chip learning and cognitive capabilities to tackle problems in machine learning and robotics. The project is also expected to provide a promising paradigm for building new generations of fault/error-tolerant computing systems

Currently, we are investigating the following issues: the communication network for medium-scale and massively-parallel neuro-inspired chips for adaptive autonomous systems, reconfigurability and adaptability methods, reliability and fault-tolerance, and learning circuits. In addition, lessons gained from this project will also be investigated to optimize power & performance of the conventional computing systems.

View this research

Dissertation and Published Works

  1. A. Ben Abdallah (Author), Advanced Multicore Systems On-Chip : Architecture, On-Chip Network, Design, Publisher: Springer, 2017, ISBN-13: 978-9811060915, ISBN-10: 98110609162017.
  2. A. Ben Abdallah (Author), Multicore Systems On-Chip: Practical Hardware/Software Design, 2nd Edition, Publisher: Atlantis, 2013, ISBN-13:  978-9491216916. 
  3. A. Ben Abdallah (Author): Multicore Systems On-Chip: Practical Hardware/Software Design, Publisher: Atlantis, 2010, ISBN 978-90-78677-22-2. 
  4. A. Ben Abdallah (Editor and one of the authors): Multicore Systems on-Chips, Publishers: Signpost, 2007, ISBN: ISBN 978-81-7895-258-1.
  1. Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model&#39;&#39;, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017,DOI: 10.1109/TVLSI.2017.2736004
  2. Achraf Ben Ahmed, Tsutomu Yoshinaga, Abderazek Ben Abdallah, "Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism&#39;&#39;,IEEE Transactions on Emerging Topics in Computing, 2017, DOI: 10.1109/TETC.2017.2737016
  3. Akram Ben Ahmed, Abderazek Ben Abdallah,&#39;&#39;Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC Systems&#39;&#39;, Jnl. of Parallel and Distributed Computing, Volumes 93–94, July 2016, Pages 30-43. DOI:10.1016/j.jpdc.2016.03.014
  4. Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems”, Journal of Supercomputing, Volume 73, Issue 4, pp 1567–1599, April 2017.doi: 10.1007/s11227-016-1846-0.
  5. Achraf Ben Ahmed, Abderazek Ben Abdallah, "Hybrid Silicon-Photonic Network-on-Chip for Future Generations of High-performance Many-core Systems", Jnl of Supercomputing, Dec. 2015, Vol. 71, Issue 12, pp 4446-4475. DOI: 10.1007/s11227-015-1539-0.
  6. Akram Ben Ahmed, A. Ben Abdallah, "Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures", Jnl of Parallel and Distributed Computing, 74/4 (2014), pp. 2229-2240.
  7. A. Canedo, A. Ben Abdallah, and M. Sowa, "Efficient Compilation for Queue Size-Constrained Queue Processors", Jnl of Parallel Computing, Vol.35, pp. 213-225, 2009. 
  8. A. Ben Abdallah, A. Canedo, T. Yoshinaga, M. Sowa, "The QC-2 Parallel Queue Processor Architecture", Jnl of Parallel and Distributed Computing, 68/2 (2008), pp. 235-245.
  9. T. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, "Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters", IPSJ Transactions on Advanced Computing Systems, Vol.46, pp.25-37, Jan. 2005. 
  10. A. Ben Abdallah, T. Yoshinaga, M. Sowa, "Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors", IEICE Transactions on Fundamental of Electronics, Communications, and Computer Science, Vol. E83-A No.12 (2000), pp.2417-2425.
Complete list of publications: