/ Tuneo Ikedo / Professor
/ Robert H. Fujii / Associate Professor
/ A. Y. Kondratyev / Associate Professor
/ Yamin Li / Associate Professor
/ Wanming Chu / Research Associate
Computer Architectrue Laboratory is organized with 7 faculty members and one visiting researcher. The followings re the summary of each members.
Multimedia Processor Architecture: Multimedia processor has been developed since 1995, which implements font, graphics, audio, video processing in a single chip of 10 million gates. we focused on the architecture design of computer graphics renderer in fine grain processing in 1996 and 30Gflop reconfigurable multimedia accelerator (coarse grain processing). The development of reconfigurable accelerator is a succession of Aizu supercomputer project. 4 graduate students and 8 undergraduate students join in this research.
1. Research: (1) Parallel Multithreaded Architecture We have examined various design issues of the parallel multithreaded architecture. A prototype of parallel multithreaded processor was designed. We are working on the performance evaluation in order to enhance the the computation capabilities of the processor. (2) Computer Arithmetic Algorithms and Implementations We have examined latency, throughput and complexity for various computer arithmetic algorithms and developed two new algorithms. The hardware designs are also finished and prototyped with FPGAs.
2. Teaching: We taught Computer Architecture (Li and Chu), Computer Organization I and Organization II (Li), and the laboratory of Logic Circuit Design (Chu). We also developed and updated two processor design projects: Sim2 processor design for the laboratory of Computer Architecture and Aizup pipeline processor design and implementation on FPGA for the laboratory of Computer Organization I. All of the teaching notes and laboratories handouts are prepared and available at Li's homepage, http://www.u-aizu.ac.jp/~yamin/.
Design Automation of Concurrenct and Asynchronous Systems: We have reached further progress in research in automation of asynchronous design, embedded reactive systems and models of concurrency. In a few research directions we continued close cooperation with Prof. A. Taubin (Computer Education Lab.) and with research groups in Cadence Berkeley Labs. (USA), Politecnico di Torino (Italy), University Politecnica de Catalunya (Barcelona, Spain) and University of Newcastle upon Tyne (England).
Research results:
1. Embedded systems and models of concurrency:
(1) We have developed a new model, called Place Chart Nets (PCN). It allows the modelling of both asynchronicity and exception handling (preemption). PCNs specify a system behavior using partial orders. PCNs have a notion of hierarchy, which is determined by preemption. PCNs is a non-trivial generalization of classical PNs, in the sense that (1) for the finite (bounded) case modeling a PCN may require an exponentially larger PN, (2) for the infinite (unbounded) case a class of PCN languages properly includes a class of PN languages and (3) k-boundedness of PCNs is decidable. (2) We developed a method for synthesis of PCNs starting from labeled transition systems. We considered applications of PCNs for design of embedded reactive systems in hardware/software codesign framework.
2. Technology mapping of speed-independent circuits:
We have reached significant progress in solving a problem of technology mapping for speed-independent circuits based on two different techniques: (1) Algebraic factorization: the proposed method performs both combinational (inserting new gates) and sequential (inserting new memory elements) decomposition of complex gates in a given standard cell library, while preserving original behaviour and speed-independence. (2) Boolean decomposition: the proposed method iteratively performs Boolean decomposition of each complex gate using Boolean relations, as opposed to the less powerful algebraic factorization approach used in previous methods. After logic decomposition, the overall library matching and optimization is carried out.
3. Testing of path delay faults:
We provided effective procedures to solve the initialization and the test pattern generation problems for the path delay fault testing of asynchronous circuits. Experimental results shows that a high level of path delay fault testability can be achieved with partial scan.
We have presented a few Invited tutorials at the Summer School, International Conference, and Fujitsu Labs.
Teaching: we taught logic design, computer architecture in the undegradute school and "Synthesis and Optimization of Digital Circuits" in the graduate school. We have lead graduation reserch projects.
This year's activities have included the design of a microcontroller controlled motorized wheelchair prototype, the design of a fuzzy logic controller using Verilog, and the design of a high speed pipeline control unit using Verilog. Implementation of the motorized wheelchair prototype into a real system which can be ridden by people with disabilities is being carried out. Analog circuit designs of various modules will be forthcoming.
My researches in 1996 are devoted to improving algorithms of the Truga001 graphics chip and modeling multimedia hyperworld. A new circuit combined Phong shading with bump mapping has been developed. Several bump-mapped shading pictures have been produced to test the developed algorithm and circuit. The interpolation method has been proposed to improve bump-mapped shading effects. Texture mapping and video mapping performance of the Truga001 has been simulated and evaluated. The hyperworld is an integration of various interaction worlds in different time, space and reality. Our research starts from basic features of the hyperworld, composition and models of an one-to-many interaction system. We are now focusing on developing the prototype of an educational hyperworld system, called Cheer.
Refereed Journal Papers