/ V. I. Varshavsky / Professor
/ Rafail A. Lashevsky / Professor
/ V. V. Smolensky / Research Associate
In 1998, the laboratory was working on research theme R21-1 "Logical Timing and Decentralized Control in Massively Parallel Computer Systems". Within the framework of this theme we were developing the general ideology of decomposing a system to Synchro-Stratum and Processor Stratum, making it possible to design GALA (Globally Asynchronous Locally Arbitrary) systems by any synchronous prototype. In some sense, the Synchro-Stratum acts like an active asynchronous clock distributed around the system.
Besides, the laboratory was studying the problems of building CMOS threshold elements and artificial neurons. This research was conducted in two directions:
Refereed Journal Papers
Summary: Using MOS-transistors with floating gate (Neuron MOS or vMOS) for building threshold logic is discussed. Two ways of vMOS threshold logic implementation, static and clocked, are under consideration. Methodology of vMOS circuit design is given. Majority voting gate (MVG) is used as an example of threshold gate with the worst conditions for getting a large number of inputs. The possibility of implementing a MVG with a certain number of inputs is the possibility of building a threshold gate with a threshold alterable in real time (from OR to AND-function) with the sum of input weights equal to the number of MVG inputs. The maximum number of threshold gate inputs is estimated depending upon the deviations of the elements dimensions and parameters inside the chip. It is shown that it is difficult to implement a static vMOS MVG with a number of inputs more than 10. For the same conditions, the number of inputs of clocked vMOS MVG is as large as many tens. A clocked vMOS threshold gate with alterable in real time input weights and threshold is proposed. Delay time and chip area for such circuits are estimated.
Summary: A novel type of CMOS threshold elements is suggested that has twice less number of transistors that the available prototype (output-wired inverters). The idea is based upon the theorem of the possibility to represent an arbitrary threshold function in the ratio form. The implementability is studied. Circuit examples are given.
Summary: A simple CMOS learnable threshold element is suggested that has only 5 MOS transistors per a learnable synapse. The implementation is based on beta-driven threshold elements. The fact that learning is provided essentially reduces the demands to the stability of the technological and circuit parameters. The results of SPICE-simulation are given for an example of learning.
Summary: Some modifications of a beta-driven artificial neuron, circuit examples and SPICE-simulation results are given.
Summary: The improved version of digital-analog CMOS implementation of an artificial neuron is discussed. This neuron is learnable to logical threshold functions, being functionally powerful and highly noise-stable. It is built on the basis of a previously suggested circuit consisting of synapses, $\beta$-comparator and output amplifier. Every learnable synapse contains 5 minimum transistors and a capacitor for storing the result of the learning. It has been shown that higher non-linearity of the $\beta$-comparator in the threshold zone can sharply increase the threshold of the realized functions and noise-stability of the neuron. To increase the minimum leap of voltage at the $\beta$-comparator output in the threshold zone which is attainable during the teaching, it is suggested to use an output amplifier with threshold hysteresis. For this aim, the neuron has three output amplifiers with different thresholds. The output of the amplifier with the middle value of threshold is the output of the neuron; the outputs of the other two amplifiers are used during the teaching. The way is suggested of refreshing the voltages (found during the teaching) on the capacitors during the evaluation process. The results of SPICE simulation prove that the neuron is learnable to most complicated threshold functions of 10 and more variables and that it is capable to maintain the learned state for a long time. In the simulation, transistor modes MOSIS BSIM3v3.1 0.8$\mu$m were used.
Summary: General problems of organizing temporal behavior in Massively Parallel Computing Systems are discussed. For the 'Globally Asynchronous Locally Arbitrary' strategy, Active Asynchronous Distributed Clock (Synchro-Stratum) is studied. Two types of logical time fields for such devices are considered which are wave and parallel fields. The transition from synchronous prototypes to Synchro-Stratum element specification is discussed.
Summary: A novel logical circuit of very fast one-two-one-track register pipeline is suggested. Its control logic provides the maximum possible throughput. This FIFO is intended for using in the Line Interface Module implementing the direct ATM-over-fiber transport mechanism.
System time has a dual nature. On the one hand, artificial systems function in natural physical time. On the other hand, the behavior of artificial systems is specified in artificial logical time. The article is devoted to the key problem of organizing temporal behavior of systems (System Timing), which is the interaction between physical and logical times. Algebraic properties of causally determined systems and the interface between physical and logical times are discussed. Decomposition of the system to Synchro-Stratum and Processor-Stratum is introduced. Synchro-Stratum is interpreted as a distributed asynchronous system clock. Hardware implementation of Synchro-Stratum is considered along with some properties of its behavior.
Summary: The sensitivity and delay of the amplifier are the key problems in the performance of Current Sensors. For large devices which consist of several cells, for example 32bit, the amplifier must react to 10-20mV. The previous type of highly sensitive amplifier which is based on cascade and reference voltage can react to this level of voltage. But this model is not stable in respect to technological and parametric variation. In this paper, we suggest a tripple cascade inverters feedbacked by an unsymmetrical pass transistor which amplifies 1mV without reference voltage. Monte-Carlo SPICE simulation shows the stableness of this model for parametric variation. We prepare the schematic of CS which includes control unit with shunt transistors and evaluate the delay.
Summary: The possibility of creating complex gates on the base of CMOS-like Wave Function Rearrangement Transistors is discussed. It is shown that when the quantum wells are connected collinearly, only self-dual Boolean functions are implemented correctly. To provide correct behavior of gates for arbitrary Boolean functions, it is suggested that the quantum wells are connected orthogonally.
Summary: MOS-transistors with floating gate (Neuron MOS-FET or vMOS) as a way to build threshold gates with parameters changeable in real time is discussed. Two types of vMOS circuits, static and clocked are under consideration. The latter is preferrable for threshold gates with a large number of inputs. The possibility of minimizing the chip area and delay time is shown for the case of using vMOS threshold gates to design VLSI neural networks with on-chip learning.