/ Omar Hammami / Associate Professor
/ Kohei Otsuyama / Assistant Professor
The performance evaluation laboratory is part of the Department of Software, the University of Aizu. The laboratory mission in the broad sense is to contribute to:
Performance Evaluation Laboratory faculty members are involved in both the Graduate School of Engineering Graduate Department of Information Systems (2nd field of studies, Computer Organization and Parallel Processing) and the Graduate Department of Computer Systems (8th field of studies, Computer Network Systems). Teachings includes: Parallel and Distributed Computer Architectures, Fuzzy and Neural Processor Design. At the undergraduate level faculty members are involved in computer architecture, performance evaluation and programming courses.
From July 1999, the Performance Evaluation Laboratory includes Dr. Hiroshi Toyoizumi. Dr. Hiroshi Toyoizumi research interests are in the study of the theories of applied probability and stochastic processes to use in performance evaluation.
The Performance Evaluation Laboratory was involved in various seminars held in the University through invited speakers.
Refereed Proceeding Papers
Neural networks simulations are notorious for being very time and resources consuming. However, although general purpose microprocessors have improved performance of these simulations, little is known on which microarchitecture features contribute the most to this performance improvement. In this context, the paper analyzes the performance impact of various microarchitectural mechanisms found in current superscalar microprocessors on the execution of a famous neural network the SOM algorithm. The conclusion is that SOM algorithm does not fully benefit from the sophisticated hardware support existing in a state of the art superscalar machine. It is especially true of the memory hierarchy as well as the branch prediction mechanisms.
The paper presents some tools based on FPGA for the purpose of computer architecture education. The main argument of the paper is that computer architecture is strongly related to several fields and therefore education in computer architecture should emphasize those links. There have been a tendancy these recent years to base computer architecture education on software tools (simulators). The author argue that FPGA reconfigurable hardware devices with their current variety presents a very attractive complementary teaching tool for computer architecture which is based on real hardware devices. This implementation aspect of the computer architecture is of prime importance despite the tendancy for increased abstraction and this due to the increasing impact of design decisions on implementations parameters like energy consumption, complexity which were recently overlooked.
This paper evaluates the contribution of various microprocessor architectural features on the execution of 4 neural networks used for classification problems.In this study, we selected the grnn, pnn, mnn and rbfn networks trained for the Iris data set and simulated with 10,000 elements datasets. Using a superscalar simulator we evaluated various architectural parameters such as IPC, memory hierarchy, branch prediction, functionnal units configuration. The main contribution of this work is to show that neural network workloads deserve their own characterization which cannot be derived from SPEC95 characteristics.
This paper describes the design and performance evaluation of a reconfigurable hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. This reconfigurable hardware is used as a coprocessor attached to a personal computer system and can be accessed through C programs. A performance evaluation and comparison have been conducted and the coprocessor implementation outperforms several software implementations on various personal computer systems.
This paper describes the hardware design design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware.
This paper proposes a system for the automatic hardware design of neural networks based on cooperative co evolutionnary paradigms and multiple reconfigurable devices. Our system is composed of logic synthesis tool, multiple reconfigurable devices and an embedded processor executing the co evolutionnary algorithm. The partitionning of the engineering design process follows current practices in hardware/sofwtare co design based on both information on arrival rate $\lambda$ of requests and the service time $\mu$ of the reconfigurable Devices. The system is suitable under some conditions for industrial applications as a reactive system but also because it can be connected to multiple systems in a totally networked industrial environment which allows download of the same hardware configuration on multiple on line devices.
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