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Performance Evaluation Laboratory


/ Omar Hammami / Associate Professor
/ Kohei Otsuyama / Assistant Professor

The performance evaluation laboratory is part of the Department of Software, the University of Aizu. The laboratory mission in the broad sense is to contribute to:

  1. Theoretical Aspects of Performance Evaluation of Computer and Communications Systems
  2. Tools and Techniques for the Performance Evaluation of Computer and Communications Systems
  3. Applications to Computer and Communications Systems : Evaluations and Performance

During fiscal year 1998 (Apr.1998 - Apr.1999) the laboratory was composed of two faculty members. Current research interests include:

  1. Project PEHW: Reconfigurable Computing Performance Evaluation Reconfigurable computing is increasingly used in various applications in telecommunications and computer systems. Our focus here is to investigate tools and techniques which allows quick performance evaluation of reconfigurable computing systems. Both analytical and simulations approach are investigated.
  2. Workload characterization of intelligent systems An increasing number of applications make use of various intelligent techniques such as: neural networks, fuzzy logic and evolutionnary computation along with their combinations. Unfortunatly, little work have been done so far on those workloads and their computationnal requirements. Our own investigations have shown that popular benchmarks such SPEC are not relevant for this type of workloads.
  3. Rapid Prototyping and Performance Evaluation using Reprogrammable Devices This research is concerned with the rapid prototyping and performance evaluation of systems using reprogrammable devices (PLD, FPGA). This is a hardware approach to performance evaluation.
  4. CoEvolvable Hardware Workbench This project addresses the problems of Cooperative coevolution using reprogrammable hardware devices.
  5. Java Virtual Machine Various issues related to JVM are currently investigated such as: Performance Evaluation of Java Virtual Machine, Performance Evaluation of Java real-machine architecture,Visualization of Java Virtual Machine for Education
  6. Performance Evaluation of Web Server
  7. Surveys on problems in Computer Mediated Communication

Performance Evaluation Laboratory faculty members are involved in both the Graduate School of Engineering Graduate Department of Information Systems (2nd field of studies, Computer Organization and Parallel Processing) and the Graduate Department of Computer Systems (8th field of studies, Computer Network Systems). Teachings includes: Parallel and Distributed Computer Architectures, Fuzzy and Neural Processor Design. At the undergraduate level faculty members are involved in computer architecture, performance evaluation and programming courses.

From July 1999, the Performance Evaluation Laboratory includes Dr. Hiroshi Toyoizumi. Dr. Hiroshi Toyoizumi research interests are in the study of the theories of applied probability and stochastic processes to use in performance evaluation.

The Performance Evaluation Laboratory was involved in various seminars held in the University through invited speakers.


Refereed Proceeding Papers

  1. Omar Hammami., Performance Impacts of Superscalar Microarchitecture on SOM Execution. 31st Annual Simulation Symposium, April 5-9, 1998, Boston, Massachusetts.

    Neural networks simulations are notorious for being very time and resources consuming. However, although general purpose microprocessors have improved performance of these simulations, little is known on which microarchitecture features contribute the most to this performance improvement. In this context, the paper analyzes the performance impact of various microarchitectural mechanisms found in current superscalar microprocessors on the execution of a famous neural network the SOM algorithm. The conclusion is that SOM algorithm does not fully benefit from the sophisticated hardware support existing in a state of the art superscalar machine. It is especially true of the memory hierarchy as well as the branch prediction mechanisms.

  2. Omar Hammami., Reconfigurable Hardware Devices Evolution: An Important Opportunity for Full Span Computer Architecture Education. WCAE98, June 27-July 1st, 1998, Barcelona, Spain.

    The paper presents some tools based on FPGA for the purpose of computer architecture education. The main argument of the paper is that computer architecture is strongly related to several fields and therefore education in computer architecture should emphasize those links. There have been a tendancy these recent years to base computer architecture education on software tools (simulators). The author argue that FPGA reconfigurable hardware devices with their current variety presents a very attractive complementary teaching tool for computer architecture which is based on real hardware devices. This implementation aspect of the computer architecture is of prime importance despite the tendancy for increased abstraction and this due to the increasing impact of design decisions on implementations parameters like energy consumption, complexity which were recently overlooked.

  3. Omar Hammami., Neural Network Classifiers Execution Characteristics on Out of Order Issue In Order Completion Superscalar Microprocessors. International Symposium on High Performance Computing '99 May 26-28, 1999, Kyoto, Japan.

    This paper evaluates the contribution of various microprocessor architectural features on the execution of 4 neural networks used for classification problems.In this study, we selected the grnn, pnn, mnn and rbfn networks trained for the Iris data set and simulated with 10,000 elements datasets. Using a superscalar simulator we evaluated various architectural parameters such as IPC, memory hierarchy, branch prediction, functionnal units configuration. The main contribution of this work is to show that neural network workloads deserve their own characterization which cannot be derived from SPEC95 characteristics.

  4. Omar Hammami., Design and Performance Evaluation of SOM on Reconfigurable Computing. 1999 Symposium on Performance Evaluation of Computer and Telecommunications Systems, Chicago, July 11-15, 1999.

    This paper describes the design and performance evaluation of a reconfigurable hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. This reconfigurable hardware is used as a coprocessor attached to a personal computer system and can be accessed through C programs. A performance evaluation and comparison have been conducted and the coprocessor implementation outperforms several software implementations on various personal computer systems.

  5. Daisuke Suzuki and Omar Hammami., SOM on Multi-FPGA ISA Board-Hardware Aspects. 6th IEEE International Conference on Electronics, Circuits and Systems, Paphos, Cyprus,Sept. 5-8, 1999.

    This paper describes the hardware design design of a multi-FPGA hardware implementation of a 16 neurons Self-Organizing Map (SOM) artificial neural network. The SOM designed includes 16 neurons controlled in a SIMD execution mode. The application targeted is 3D to 2D projection. The clock frequency of the hardware design is 11.386 MHz and it has been implemented on 5 xilinx FPGA chips mounted on a plug-an-play PC ISA board. The resulting hardware outperforms under some conditions several software simulations implementations running on various PC hardware.

  6. Omar Hammami, Kenchi Kuroda, Qiangfu Zhao and Kazayuki Saito., CoEvolvable Hardware Platform for Automatic Hardware Design of Neural Networks. IEEE International Conference on Industrial Technology, 2000.

    This paper proposes a system for the automatic hardware design of neural networks based on cooperative co evolutionnary paradigms and multiple reconfigurable devices. Our system is composed of logic synthesis tool, multiple reconfigurable devices and an embedded processor executing the co evolutionnary algorithm. The partitionning of the engineering design process follows current practices in hardware/sofwtare co design based on both information on arrival rate $\lambda$ of requests and the service time $\mu$ of the reconfigurable Devices. The system is suitable under some conditions for industrial applications as a reactive system but also because it can be connected to multiple systems in a totally networked industrial environment which allows download of the same hardware configuration on multiple on line devices.

Grants

  1. Omar Hammami, General Research, (A), Ministry of Education , Science, Sports and Culture of Japan Scientific Research Fund, Research Title: EBPU. No. 10750283, April 1999.

  2. Omar Hammami, Kenichi Kuroda, Kazayuki Saito and Qiangfu Zhao., (C),General Research, Ministry of Education, Science, Sports and Culture of Japan Scientific Research Fund,, Research Title: CCEA. No. 10650375, April 1999.

Academic Activities

  1. Omar Hammami., SCS,32nd Annual Simulation Symposium, San Diego, California. Program Committee Member. April 1999.

  2. Omar Hammami., SCS,33rd Annual Simulation Symposium, Washington, D.C.. Program Committee Member. April 2000.

  3. Omar Hammami., IEEE, Workshop Parallel Execution on Reconfigurable Hardware, Program Committee Member. September 1999.

  4. Omar Hammami., Referee 7th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS'99), College Park, Maryland, 24-28 October, 1999.

  5. Omar Hammami., SCS, Annual Simulation Symposium Program Committee Member. April 1999.

  6. Omar Hammami., SCS, Annual Simulation Symposium Program Committee Member. April 2000.

  7. Omar Hammami., IEEE, PERH99 Program Committee Member. September 1999.

Others

  1. Omar Hammami., Organization of the PERH99 Workshop in conjunction with ICPP99. September 1999.



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November 1999