Computer Networks Laboratory

/ V. B. Marakhovsky / Professor
/ Yaoxue Zhang / Visiting Professor
/ Zi Xue Cheng / Assistant Professor
/ Kshirasagar Naik / Assistant Professor

Computer Networks Laboratory is working in four directions within Research Projects and Top-Down Education Course-ware Development Projects:

1. Logical-timing and Decentralized Control in Computing Systems;
2. Network-based Computing and Distributed Computing;
3. Protocol Engineering and Conformance Testing;
4. Groupware

• 1.1 Global Synchronization of Asynchronous Arrays in Logical Time: Our approach is decomposing the asynchronous array to synchro-stratum which acts as a distributed asynchronous clock and automata stratum whose automata have a construction similar to that of the synchronous prototype array. For various disciplines of prototype synchronization, the corresponding variants of synchro-stratum implementation are developed.

• 1.2 One-Two-One Track Asynchronous FIFO: A novel logical circuit of very fast one-two-one-track register pipeline is suggested. Its control logic provides the maximum possible throughput This FIFO is intended for using in the Line Interface Module implementing the direct ATM-over-fiber transport mechanism.

• 1.3 Beta-CMOS implementation of artificial neuron: The improved version of digital-analog CMOS implementation of an artificial neuron is suggested. This neuron is learnable to logical threshold functions, being functionally powerful and highly noise-stable. It is built on the basis of a previously suggested circuit consisting of synapses, $\beta$-comparator and output amplifier. It has been shown that higher non-linearity of the $\beta$-comparator in the threshold zone can sharply increase the threshold of the realized functions and noise-stability of the neuron.

• 2.1 Design of a Multicast Protocol for Mobile Computing We study the problems in designing multicast protocol in a mobile environment. Considering both the problems in mobile computing and efficiency, we design a multicast protocol for single-source ordering.

• 2.2 Design of a distributed algorithm for solving competition among process groups Resource allocation is a fundamental problem in distributed systems. Many deadlock-free and starvation-free distributed algorithms have been developed for the resource allocation. However, with the progress of computer networks, a various of group activities over computer network by using groupware become possible and required. When many groups are using the same network resources, competition for resources may happen among group. Even though the deadlock and starvation never happen, the GROUP DEADLOCK and GROUP STARVATION may happen. The new type of problems are very difficult solved by existing algorithms. In this paper, we propose a new algorithm for resolving the competition among groups.

• 3.1 Protocol Specification Support: In order to automate the development of protocols, we investigated methods to support the development of protocol specification based on formal description technique LOTOS.

• 3.2 Efficient and Reliable Testing of Communication Protocols: We have developed methodologies to efficiently generate test sequences, and proposed new features of test architectures to incorporate the idea of reliability into a test method.

Refereed Journal Papers

1. Z. Cheng and T. Huang., An Extension of Committee Coordination Problem and Its Decentralized Solution. Chinese Journal of Electronics. vol.7, No.4, pp.322--327, 1998.

   In this paper, we proposed a new method for coordinating meetings.

2. Y. Wata, Z. Cheng, and S. Noguchi. Distributed Algorithms for Allocation of Resources to Process Groups and Their Complexity. IEICE Trans. on Information and Systems, vol.J81-D-I, No.6, pp.651-665, 1998.

   In this paper, we proposed two algorithms for resource allocation among groups and the comparison of their complexities.

3. K. Naik, Z. Cheng, and D. Wei., Distributed Implementation of the Disabling Operator in LOTOS. Information and Software Technology, vol.41, No.3, 1999.

   In this paper, we proposed a new distributed implementation method for Disabling Operator in LOTOS.

4. M. Osano, M. A. M. Capretz, and Z. Cheng., A Dynamic Model for Cooprative Agents with Different Goals. 3Dforum, vol.12, No.3,1998.

   In this paper, we proposed a new model for cooprative agents with different goals.

1. Varshavsky, V.; Marakhovsky, V., One-Two-One Track Asynchronous FIFO. Proceedings of the 1998 IEEE Asia-Pacific Conference on Circuits and Systems, Theme: Microelectronicss and Integrating Systems (APCCAS-98). pp.743--746, IEEE Press, Chiangmai, Thailand. November 1998.

   A novel logical circuit of very fast one-two-one-track register pipeline is suggested. Its control logic provides the maximum possible throughput. This FIFO is intended for using in the Line Interface Module implementing the direct ATM-over-fiber transport mechanism.

2. Varshavsky, V.; Marakhovsky, V., Beta-CMOS implementation of artificial neuron. SPIE's 13th Annual International Symposium on Aerospace/Defense Sensing, Simulation, and Controls. Applications and Science of Computational Intelligence II, pp.210--221, SPIE, Orlando, Florida, April 1999.

   The improved version of digital-analog CMOS implementation of an artificial neuron is discussed. This neuron is learnable to logical threshold functions, being functionally powerful and highly noise-stable. It is built on the basis of a previously suggested circuit consisting of synapses, $\beta$-comparator and output amplifier. Every learnable synapse contains 5 minimum transistors and a capacitor for storing the result of the learning. It has been shown that higher non-linearity of the $\beta$-comparator in the threshold zone can sharply increase the threshold of the realized functions and noise-stability of the neuron. To increase the minimum leap of voltage at the $\beta$-comparator output in the threshold zone which is attainable during the teaching, it is suggested to use an output amplifier with threshold hysteresis. For this aim, the neuron has three output amplifiers with different thresholds. The output of the amplifier with the middle value of threshold is the output of the neuron; the outputs of the other two amplifiers are used during the teaching. The way is suggested of refreshing the voltages (found during the teaching) on the capacitors during the evaluation process. The results of SPICE simulation prove that the neuron is learnable to most complicated threshold functions of 10 and more variables and that it is capable to maintain the learned state for a long time. In the simulation, transistor modes MOSIS BSIM3v3.1 0.8$\mu$m were used.

3. Varshavsky, V.; Marakhovsky, V., Learning Experiments with CMOS Artificial Neuron. Lecture Notes in Computer Science 1625, Computational Intelligence Theory and Applications, ed. by Bernard Reusch. Proceedings of the 6th Fuzzy Days International Conference on Computational Intelligence, pp.706--707, Springer, Dortmund, Germany, May 1999.

   Learning experiments with digital/analog artificial neuron by SPICE-simulation for limiting values of the parameters (such as the sum of input weights and/or threshold) requires long time that largely depends on the length of the learning (test) sequence. We suggest to use as test functions a class of threshold functions the minimum forms of which can be represented in accordance with Gorner's scheme (Gorner's functions). These functions have shortest teaching sequences and provide the neuron parameters close to the biggest ones for a given number of variables. For Gorner's function of $n$ variables the values of the variable weights and threshold form the Fibonacci sequence (1, 1, 2, 3, 5, 8, 13, 21, 34, 55, 89, 144, 233 ...) with the length of a unit learning sequence equal to $n+1$.

4. Varshavsky, V.; Marakhovsky, V., Beta-CMOS Artificial Neuron and Implementability Limits. Lecture Notes in Computer Science 1607, Engineering Applications of Bio-Inspired Artificial Neural Networks, Vol.11. pp.117--128, International Work-Conference on Artificial and Natural Neural Networks (IWANN'99), Springer, Spain, June 1999.

   The paper is focused on the functional possibilities (class of representable threshold functions), parameter stability and learnability of the artificial learnable neuron implemented on the base of CMOS $\beta$-driven threshold element. A neuron $\beta$-comparator circuit is suggested with a very high sensitivity to input current change that allows us to sharply increase the threshold value of the functions. The SPICE simulation results confirm that the neuron is learnable to realize threshold functions of 10, 11 and 12 variables with maximum values of threshold 89, 144 and 233 respectively. A number of experiments were conducted to determine the limits in which the working parameters of the neuron can change providing its stable functioning after learning to the functions for each of these threshold values. MOSIS BSIM3v3.1 0.8$\mu$m transistor models were used in the SPICE simulation.

5. Varshavsky, V.; Marakhovsky, V., The Simple Neuron CMOS Implementation Learnable to Logical Threshold Functions. Proceedings of International Workshop on Soft Computing in Industry'99 (IWSCI'99), pp.463--468, IEEE, Muroran, Hokkaido, Japan, June 1999.

   The problem of hardware implementation of artificial neuron in CMOS technology is discussed. The neuron is constructed on the base of $\beta$-driven threshold element consisting of $\beta$-comparator and output amplifier. The $\beta$-comparator circuit is improved to provide a very high sensitivity to current change that allows to sharply increase the function threshold value. The full circuit of the learnable synapse consists of 5 transistors and capacitor. The neuron contains three amplifiers with different input threshold that improves its learnability. SPICE simulation confirms that the neuron is learnable to realize the most complex threshold functions of 10 and more variables. Some simulation results of teaching process of the neuron to implement the certain threshold function of 10 variables with threshold equal to 89 are given.

6. Z. Cheng, Naka Tajima, and Shoichi Noguchi., l-coterie: A New Generalization Coterie for Decentralized Consensus. The 12th International Conference on Information Networking (ICOIN--12), IEEE Computer Society. Jan. 1998.

   In this paper, we proposed a new coterie for decentralized consensus problem.

7. Z. Cheng and Qian-Ping Gu., Distributed Algorithms for Leader Election on Partially Ordered Keys. IPSJ Symposium Series Vol.98. No.14, Information Processing Society, Japan, IPSJ. Nov. 1998.

   In this paper, we proposed distributed algorithms for leader election on partially ordered keys.

8. M. Murakami, Y. Wada, and Z. Cheng., Distributed Algorithms for Resource Allcation to Partial Processes of a Group. IPSJ Symposium Series Vol.98. No.14, IPSJ. Nov. 1998.

   In this paper, we proposed a new solution for distributed resource allocation among process groups.

9. K. Komine, K. Hirai, S. Nakamura, and Z. Cheng., Implementation and Evaluation of the Meeting Scheduling Method based on Concession of Available Times. IPSJ Symposium Series Vol.98. No.14, IPSJ. Nov. 1998.

   In this paper, we proposed a new meeting scheduling method.

10. R. Murakami, Y. Saitou, K. Hirooka, and Z. Cheng. Design of a Support System for Gathering and Circulating Information on Internet. IPSJ Symposium Series Vol.98. No.14, IPSJ, Nov. 1998,

    In this paper, we proposed a new method for gathering and circulating information on Internet.

11. S. Nakamura, K. Sato, and Z. Cheng., A Support Method for Assignment based on Psychological Persuasion Mechanism among Agents. IPSJ Symposium Series Vol.98. No.14, IPSJ, Nov.1998.

    In this paper, we proposed a new method for assignment problem by using agents.

1. Vyacheslav B. Marakhovsky. Member of ACM.

2. Vyacheslav B. Marakhovsky. Member of IEEE. 1998.