/ V. I. Varshavsky / Professor
/ Rafail A. Lashevsky / Professor
/ V. V. Smolensky / Research Associate
The Computer Logic Design Laboratory carried out the following Research Projects:
In 1996, the major directions and results of the work on these projects were:
1. Data-Controlled Delays in the Asynchronous Design. In order to increase the efficiency of using padding delays to produce signals of transient process completion, we suggest to use data-controlled incorporated delays in the cases when the variations of transient process duration are determined by the sets of input signal values. Data controlled delay is illustrated by an example of adder design.
2. Asynchronous Control Device Design by Net Model Behavior Simulation. The design is based on the compilation of standard circuit modules corresponding to PN fragments into a net modeling PN behavior. Modifications of the known modules, a number of new module types, and the procedures of minimization are developed.
3. Hardware Support of Discrete Event Coordination. To build asynchronous control circuits that coordinate process interaction, the method of direct translation of interact specification using Petri nets is being developed.
4. Towards Self-Checking and Self-Recovery in Self-Timed Embedded Systems. A general trend in design of embedded systems is an increasing role of hardware in providing their main functionality. Classical hardware designs for dependability use clock and are dependent on the clock distribution logic, which itself becomes more complex. Asynchronous circuits are posed as a promising alternative for embedded systems. Self-timed designs offer inherent self-checking properties due to their ability to acknowledge the completion of transient processin subcomponents.
5. Self-Timed Data Transmission in Massively Parallel Computing Systems. The current sensor with wide range of the measured current is suggested. The principles of control in circuits with current sensors are developed. Self-timed transmission/reception circuits with single-wire bit handshake are suggested which allow to transmit combinations of n-bit code by n+2 communication lines.
6. Global Synchronization of Asynchronous Arrays in Logical Time. Our approach is decomposing the asynchronous array to synchro-stratum which acts as a distributed asynchronous clock and automata stratum whose automata have a construction similar to that of the synchronous prototype array automata. For various disciplines of prototype synchronization, the corresponding variants of synchro-stratum implementation for the asynchronous analogue are developed.
7. vMOS Threshold Gates. Using MOS-transistor with floating gates (vMOS) for building threshold logics is invesigated. Design methodology for static and clicked vMOS circuits is developed. Threshold gate with alterable input weights and threshold is proposed.
8. Logic Design for Nanoelectronics. The problems are considered which occur in logical design of the next generation of integral circuits based on quantum devices and nanotechnology.
Refereed Journal Papers
Using MOS-transistors with floating gate (neuron MOS) for building threshold logic is discussed. Two ways of implementation - static and cdlocked - are under consideration. Methodology of circuit design is given. The maximum number of threshold gate inputs is estimated depending upon the deviations of the elements dimentions and parameters inside the chip. It is shown that it is difficult to implement the static majority votin gate with number of inputs more than 10. For the same conditions, the number of inputs of clocked neuron MOS is many tens. A clocked neuron MOS threshold gate with changable in real time input weights and threshold is proposed. Delay time and chip area are estimated.
A novel circuit for a first order filter of signals that use pulse-duration modulation is suggested. The filter contains one counter of the reference frequency with a variable count modulus and a control circuit instead of usually used structure of two reference frequency counters and a microprocessor.
Permanent-prechargeable amplifiers are suggested for using in current sensors. This considerably improves the characteristics of CS and makes it possible to remove some known shortcomings of CS.
General problems of introducing time in artificial systems are discussed. The methodology of decomposing the system to Synchro-Stratum and Processor-Stratum is being developed. This makes possible to form the logical system time independently and provide its interface with the physical time. An example of Synchro-Stratum hardware implementation is given.
Circuits on threshold elements have aroused considerable interest in recent years. One of the possible approaches of their implementation is using output wired CMOS invertors. The model of such an element is a CMOS pair with variable beta of fully open p- and n-transistors. This model is specified by the ratio form of threshold function. It has been proved that any threshold function can be rewritten in ratio form. This gives us an evident way of beta-driven implementation of threshold functions. The analysis of beta-DTE implementability, examples of circuits and results of their SPICE simulation are given.