Asynchronous circuits are robust to the variations of parameters (voltage level, temperature, delay parameters migration, arbitration phenomenon). Moreover, they have self-checking properties with respect to stuck-at faults at the outputs of the logic gates. However the output stuck-at fault model can not ensure correct circuit operation in the presence of real, physical defects on a chip.
The latest result in the testing of asynchronous circuits are very promising, because cover the most realistic logic model of physical defects.