The PMSP is a multiple-instruction-stream multiple-execution-pipeline processor capable of improving processor throughput by exploiting instruction level parallelism. We have finished the datapath design which includes ALU/Shifter, floating-point adder/subtracter, multiplier, divider, squire rooter, and floating-point integer converter. Some parts have been verified with FPGAs. We are working on designing the control unit, Verilog simulation, and performance evaluation.