/ V. I. Varshavsky / Professor
/ Rafail A. Lashevsky / Professor
/ V. V. Smolensky / Research Associate
The Computer Logic Design Laboratory is carrying out the following Research Projects and Top-Down Education Courseware Development Projects:
In 1995, the major directions and results of the work on these projects were:
1. Asynchronous Interfaces.
The design of a speed-independent communication channel based on a pipeline token-ring architecture is described. This approach can help reduce some negative "analogue" effects inherent in asynchronous busses (including on-chip ones) by means of using only "point-to-point" interconnections. We outlined the major ideas of the channel organization, protocol and our syntax-driven implementation of the channel protocol controller.
2. Asynchronous Event Control Design Using Simulating Circuits.
To build asynchronous control circuits that coordinate process interaction, the method of direct translation of interact specifications using Petri nets is being developed. Modifications of the known modules and a number of new modules modeling fragments of Petri nets are given. These modules considerably improve the quality of the obtained solutions.
3. Data-Controlled Delays in the Asynchronous Design.
We suggested to use data-controlled incorporated delays in the cases when the variations of transient process durations are determined by the sets of input signal values. The control over the value of an incorporated delay is illustrated by an example of asynchronous adder design.
4. Decentralized Distributed Resources Allocation in Massively Parallel Computing Systems.
We discussed a mathematical framework and logical strategy of optimization for the organization of resource sharing to attain global maximum in computer performance when we have limited resources, such as common memory, channels and so forth.
5. Quantum Devices: New Possibilities & New Problems.
Using novel physical principles and technology development, on the one hand, provides new logical and architectural possibilities but, on the other hand, poses a lot of new problems. By the examples of Tunneling Resonant Transistors, Quantum Dot Cells and CMOS-like Quantum Devices, these possibilities are demonstrated along with some problems to be solved for their efficient usage.
6. VMOS circuitry.
Tolerance of threshold logical Circuits based on Transistors with Floating Gate is analyzed. It is shown how the possible number of threshold gate inputs depends on design rules and process variation. The recent technology processes allow one to create new logic circuitry with decreasing chip area.
Refereed Journal Papers
A procedure of designing a self-timed device defined by the model of finite automaton is suggested. In accordance with the chosen automaton standard implementation structure from the automaton transition/output graph one derives the Signal Graph Specification that then is processed by the formal synthesis procedure for self-timed implementation. The design procedure is illustrated by two examples: Stack Memory and Counter with Constant Acknowledge Delay.
Current sensor with wide range of the measured current is suggested. The principles of control in circuits with current sensors are developed. Self-timed data exchange between local processes of the system is discussed. Transmission/reception circuits with single-wire bit handshake are demonstrated. Their transmission rate is no worse than that of double-wire circuits. They allow one to transmit combinations of $n$-bit code by $n+2$ communication lines.
Here is the development of the idea of decomposing an array to the array as such (its synchronous prototype, modified in one way or another to organize timing handshake) and Synchro-Stratum which functions as a distributed asynchronous clock suggested in [a,b,c]. We consider various disciplines of prototype timing and the corresponding Synchro-Stratum implementation.
Using novel physical principles and technology development, on the one hand, provide new logical and architectural possibilities and, on the other hand, pose a lot of new problems. By the examples of Tunneling Resonant Transistors, Quantum Dot Cells and CMOS-like Quantum Devices, these possibilities are demonstrated along with some problems to be solved for their efficient usage.
We discuss a mathematical framework for the organization of resource sharing to attain global maximum in computer performance when we have limited resources, such as common memory, channels and so forth. Local strategy of optimization is considered that leads to the optimal distribution of common resources.
Asynchronous design technique has an approach of using padding delays to produce signals of transient process completion. In order to increase the efficiency of this approach, we suggest to use data-controlled incorporated delays in the cases when the variations of transient process durations are determined by the sets of input signal values. The control over the value of an incorporated delay is illustrated by an example of asynchronous adder design. The results of PSPICE simulation confirm the efficiency of this approach.
The impossibility of asynchronous implementation of the indivisible operation of marking change at the circuit level leads to the necessity of modelling PN with modified rules of marking change. Modifications of the well-known modules are given that minimize the procedures and a number of new module types and the rules of their connection that considerably improve the quality of the obtained solutions in terms of both speed and area.
An approach to design asynchronous systems that coordinate concurrent discrete events of an arbitrary physical nature is discussed. To build asynchronous control circuits that coordinate process interaction, the method of direct translation of interact specifications using Petri nets is being developed. Modifications of the known modules and a number of new modules modeling fragments of Petri nets are given. These modules considerably improve the quality of the obtained solutions. The design ``reefs'' are fixed. The minimization procedures are associated with a change of marking change rules.
The problem of global synchronization is solved for asynchronous processor arrays and multiprocessor systems with an arbitrary interconnection graph. Global synchronization of asynchronous systems is treated as a homomorphic mapping of an asynchronous system behavior in logical time onto the behavior of the corresponding synchronous system with a common clock functioning in physical time. The solution is based on decomposing the system to the processor stratum and synchro-stratum; the latter plays the role of a global asynchronous clock. For the case of a synchronous system with two-phase master-slave synchronization, a simple implementation of the synchro-stratum for the corresponding asynchronous system is proposed. It is shown that, depending on the local behavior of the processors, the synchro-stratum is able to perform two types of global synchronization: parallel synchronization and synchronization that uses a system of synchro-waves.
If the system modules that realize local processes are not asynchronous and implemented in CMOS-technology, then, to detect the moments of the transient processes completion in them, the idea of current indication is used. A circuit of a current sensor is suggested with wide range of permissible changes of the measured current and with admissible characteristics. Two ways of organizing the interaction between circuits with current sensors are developed. The principles of self-timed data exchange between local processes of the system and data transmission by means of a dual-rail code and binary code with handshake for every bit are considered. The possibility of organizing single-wire bit handshake is demonstrated and its self-timed implementation is developed with the transmission rate no worse than that of double-wire bit handshake.
General problems of global synchronization of asynchronous arrays are considered. The conception of logical timing and system decomposition to synchro-stratum and processor stratum is developed.
We describe the design of a speed-independent communication channel based on a pipeline token-ring architecture. We believe that this approach can help reduce some negative "analogue" effects inherent in asynchronous buses (including on-chip ones) by means of using only "point-to-point" interconnections. We briefly outline the major ideas of the channal's organization, protocol and our syntax-driven implementation of the channel protocol controller. The protocol has been recently verified for deadlock-freedom and fairness.
An approach to design asynchronous systems that coordinate concurrent discrete events of an arbitrary physical nature is discussed. To build asynchronous control circuits that coordinate process interaction, the method of direct translation of interact specifications using Petri nets is being developed. Modifications of the known modules and a number of new modules modeling fragments of Petri nets are given. These modules considerably improve the quality of the obtained solutions. The design ``reefs'' are fixed. The minimization procedures are associated with a change of marking change rules.
Is the design methodology of logical and computing structures ready to efficiently use new functional possibilities of quantum devices? Does the range of existing and suggested quantum devices provide effective design of logical and computing structures? With some examples, we discuss the possibility of obtaining positive answers to these questions uniting the efforts of physicists, technologists and experts in computer engineering. A number of hot points is outlined where this collaboration may be fruitful.