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PMSP -A22 Parallelly Multithreaded Superscalar Processor

Yamin Li,
Associate Professor, Computer Architecture Laboratory
Tuneo Ikedo,
Professor, Computer Architecture Laboratory

PMSP is a multiple-instruction-stream multiple-execution-pipeline processor capable of improving processor throughput by exploiting instruction level parallelism. We have finished the architecture and organization description, developed a performance prediction model, and designed the datapath. Now, we are working on designing the control unit, putting all the circuits together, attempting to reduce the amount of gates required, and developing the instruction scheduling strategy from compiler's point of view.


www@u-aizu.ac.jp
January 1996