Computer Devices Laboratory

/ Kazuyuki Saito / Professor
/ Yasuhiro Hisada / Assistant Professor

The Computer Devices Laboratory (CDL) focuses on education and research in VLSI technologies and related areas. The main activities are as follows:

Education:

• Physics of Semiconductor Devices
• Microelectronics Analog and Digital Circuit Technologies for VLSI
• VLSI Design

(1) Devices and Process Technologies for VLSI (2) VLSI Architecture

The CDL established a framework for computer-assisted education for the above fields. The following shows software for this purpose.

• Process Simulation: VEGA
• Topography Simulation on VLSI Structures: PARADISE
• Device Simulation: VEGA
• Parameter Extraction for SPICE from VEGA: PARAM
• Parameter Extraction for SPICE from Actual Devices: ICCAP
• Circuit Simulation: Cadence SPICE and pSPICE
• VLSI Architecture: Cadence Design Entry System

CDL performs the following two Top-Down Education Projects at University of Aizu.

• Microelectronics-II Courseware
• Courseware Development for VLSI Design Education

The computer devices laboratory and the computer solid state physics laboratory jointly proposed a facility for physical and chemical experiments for Solid State Physics education and VLSI education. The proposal was accepted and the planning details are now in progress.

Research:

The main objective of research in the CDL is to develop a new environment for VLSI design and diagnoses. This will be an intelligent manufacturing system for VLSIs, including statistical representation, topographic representation, and expert system representation of VLSI design and diagnoses. The objects of representation are not restricted in the devices and processing technologies but will cover manufacturing system modeling to the reliabilities of VLSI.

The research projects being performed in the CDL are as follows:

• Representation of VLSI Technology on Computer: Group Research Development Project of the University of Aizu.
• Research on Parameter Extraction for VLSI Simulation: with NTT LSI Laboratories.
• Research on Precise Modeling for T-CAD: with two laboratories from NTT, companies, and universities.

Others:

Prof. K. Saito is a member of the following research committees. (1) Research for Improvement in the Education of VLSI System Design in the University (2) Preparatory Committee for a Research Center on VLSI Design and Fabrication

Dr. K. Saito, Dr. Y. Hisada, and Mr. K. Nakazawa (in the Center for Cultural Research and Studies) organized a research project on Psi Energy as an extracurricular student research project (SCCP), to create a measurement system to monitor signals from the human body.

Refereed Journal Papers

1. T. Abe, S. Tazawa, and K. Saito. Optimization of via-hole shape using quasi-3-d topography simulation. Electronics and Communications in Japan, 77(2):106--115, 1994.

   Deposition and etching rates exhibit localized change in via-holes because the incoming particles are shielded in three dimensional topography. To investigate this problem, quasi-3-D topography simulation is applied, approximating the shape of the via-holes in LSI using rectangular or elliptical functions. Parameters controlling reactions during via-hole formation are extracted, and the fabrication of via-holes is optimized using the simulator.

1. K. Saito. A study on VLSI facility design. In 150th Meeting on SICE. SICE, Tohoku Chapter, 1994.

2. K. Saito, Y. Sato, N. Yabumoto, and Y. Honma. Trap of hydrogen in as ion-implanted-defects. In Extended Abstracts for 42nd Spring Meeting. The Japan Society of Applied Physics, 1995.

3. N. Yabumoto, Y. Honma, Y. Sato, and K. Saito. Detection on ion-implanted impurities b, p, as by tds. In Extended Abstract for 42nd Spring Meeting. The Japan Society of Applied Physics, 1995.

1. Kazuyuki Saito and T. Iizuka. Investigation of facilities for physics and chemistry experiments. Technical Report 94-2-004, University of Aizu, 1994.

2. Kazuyuki Saito, M. Ershov, T. Iizuka, and V. Ryzhii. English-japanese mini-dictionary--general physics, semiconductor, microelectronics, version 1.0. Technical Report 95-2-001, University of Aizu, 1994.

1. S. Tazawa. Research on VLSI Process Simulation Technology , University of Osaka Prefecture, 1994. Thesis Advisor: Kazuyuki Saito.

1. Kazuyuki Saito and C. Hashimoto, Spring 1994. Japan Patent Registered: Fabrication Technology for Semiconductor Devices, Japan Patent No.1809060.

2. Kazuyuki Saito and C. Hashimoto, Spring 1994. Japan Patent Registered: Fabrication Technology for Semiconductor Devices, Japan Patent No.1809061.

3. Kazuyuki Saito and C. Hashimoto, Spring 1994. Japan Patent Registered: Fabrication Technology for Semiconductor Devices, Japan Patent No.1809062.

1. T. Nanya, Kazuyuki Saito, and et al. Research for improvement in the education of VLSI system design in the university continued from 1994. University fund, VLSI system design, 1994.

2. Kazuyuki Saito. Grant from NTT, Research on Parameter Extraction for VLSI Simulation. Company fund, VLSI Simulation, 1994.

1. Kazuyuki Saito, University of Tokyo, Spring 1994. Member of the preparatory committee for ``Research Center on VLSI Design and Fabrication, ( Committee chairman Prof. K. Ho).

2. Kazuyuki Saito, Journal of the Electrochemical Society, Spring 1994. Referee.

1. Kazuyuki Saito, Spring 1994. Give a seminar on MOS VLSI Process Design for NTT Co. and NTT Advance Technology Co.